This release note describes ABI issues, known problems and reminders for users
of the first public release of the TASKING VX-toolset for ARM.
The following parts are described:
The tools support architectures ARMv4, ARMv4T, ARMv5T, ARMv5TE and XScale. The Jazelle extension of the ARMv5TE architecture (ARMv5TEJ) is supported only by the assembler, i.e. the bxj instruction is supported. There is no support yet for Vector Floating Point (VFP).
The C++ compiler is not part of this release.
Compatibility with ARM RVCT v2.2 assembly
The assembler supports the pseudo-instructions defined by ARM RVCT v2.2 tools, including the POP, PUSH, LSL, LSR, ASR, ROR and RRX instructions for ARM state.
The assembler accepts the condition code as the last element of any mnemonic.
When the --relaxed option is switched on the assembler accepts 2-operand versions of 3-operand instructions when the first and second operand are a destination and a source register and the same register is used for both, e.g. 'add r1,r1,r3' may be written as 'add r1,r3' and 'add r1,r1,#4' may be written as 'add r1,#4'.
The assembler does not accept that both registers are specified for double-word memory access instructions. An instruction pair is specified by its even register.
The user should not add 1 to Thumb(R) label expressions in literal pools or data sections. This will be taken care of automatically by the assembler and the linker.
The assembler (and the linker) do not emit mapping symbols ($a, $d and $t) to mark address ranges containing ARM code, data or Thumb code respectively. This implies that in some situations the debugger does not correctly disassemble the code.
The linker automatically generates ARM-Thumb interworking veneers when needed. This release always creates a long veneer, i.e. short veneers and inline veneers are not used. Veneer symbol names do not follow the convention proposed by the EABI (not mandatory).
The linker does not generate long-branch veneers for out-of-range function calls by default. This feature can be enabled through the --long-branch-veneers option, but care should be taken. The option slows down the linking process considerably and it can lead to larger code size even when veneers are not needed after all. It is better to prevent long branches and only to use the option when long branches cannot be .
All product libraries are compiled for ARM-Thumb interworking.
The startup code for ARM and Thumb (cstart.asm and cstart_thumb.asm) included in the C-library provide basic functionality: it initialises the stack pointer, copies global data from ROM to RAM, calls the application's main function and calls the exit function upon return from main. It does not do any hardware initialisation. The user can copy the startup source code from the library to his own project and modify it in order to meet specific hardware needs such as the initialisation of special function registers or setting specific bits in the status register. You may contact Altium Support for assistance on hardware-specific issues pertaining to the use of the TASKING VX-toolset.
The CrossView Pro instruction set simulator debugger is provided with this release.
The debugger recognizes register alias names IP, SP, LR and PC for general purpose registers R12, R13, R14 and R15. The aliases can be displayed in the register window. The disassembler only shows the general purpose names.
The disassembler does not recognize literal pools (data pockets) inside code sections. It will try to disassemble the constants in a pool. The value of the constants can be viewed by switching on hexadecimal opcode display through the source window setup.
Copyright 2004-2006 Altium BV