TASKING VX-toolset for ARM



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This release note describes ABI issues, important developers notes and changes and new features with respect to version v1.1r1, v1.1r2, v1.1r3, v1.1r4  & v1.1r5 of the TASKING VX-toolset for ARM.

The following parts are described:

The tools support architectures ARMv4, ARMv4T, ARMv5T, ARMv5TE and XScale. The Jazelle extension of the ARMv5TE architecture (ARMv5TEJ) is supported only by the assembler, i.e. the bxj instruction is supported. There is no support yet for Vector Floating Point (VFP).


Startup code, vector table & separate stack pointers for each processor mode (since version 1.1r2)

The startup code and  the way the vector table is created is substantially improved since version 1.1r2. Please read the concerning chapter Run-time Environment of the ARM Embedded Tools Reference for a full overview of the new situation.

Alignment of composite types (since version 1.1r2)

The alignment of composite types is changed from optimal to natural to be in line with the EABI. You can set the optimal alignment with the compiler option --align-composites

FIQ & IRQ interrupts disabeled (since version 1.1r4)

Since version v1.1r4 the default configuration for FIQ and IRQ interrupts is changed from enabled to disabled. This involves the default EDE options and the arm.lsl file.


C++ compiler available since version 1.2r1

Version 1.2r1 of the TASKING VX-toolset for ARM optionally includes a C++ compiler.

The C++ compiler accepts the C++ language of the ISO/IEC 14882:1998 C++ standard (with some minor exceptions) and can be seen as a preprocessor or front end which accepts C++ source files or sources using C++ language features. The output generated by the C++ compiler is C, which can be translated by the C compiler. The C++ compiler also accepts embedded C++ language extensions.


New compiler options (since version 1.1r2)

 Option Description
--call-info Generate info for call graph
--align-composites Set the alignment for composite types (structs, unions and arrays)

New (function) qualifiers and attributes (since version 1.1r2)

Keyword Description
__novector Do not generate the exception vector
__interrupt_iabt Define exception handler for a prefetch abort
__interrupt_dabt Define exception handler for a data abort
__interrupt_und Define exception handler for an undefined instruction
__unaligned Suppress the alignment of objects or structure members
__packed__ Prevent alignment gaps in structures

Complex support (since version 1.1r3)

Added support for complex (and imaginary) types and arithmetic.

New function qualifier for exception handlers (since version 1.1r3)

Keyword Description
__nesting_enabled This function qualifier can be used for exception handlers to force the function prolog to save the link-register and to enable interrupts.


__interrupt_swi __nesting_enabled void swi( int n )
        if (n==2) __swi(3);

New SFR files (since version 1.1r5)

Added SFR files for NXP, STMicroelectronics and Samsung.


.code16 & .code32 (since version 1.1r2)

The .code16 and .code32 directives are useful when you have files that contain both ARM and Thumb instructions. Since version 1.1r2 the handling by the assembler of those directives has slightly changed. The directives must now appear before the instruction set change and between a .SECTION/.ENDSEC. The default instruction set at the start of a section depends on the use of assembler option --thumb.

Compatibility with ARM RVCT v2.2 assembly

The assembler supports the pseudo-instructions defined by ARM RVCT v2.2 tools, including the POP, PUSH, LSL, LSR, ASR, ROR and RRX instructions for ARM state.

The assembler accepts the condition code as the last element of any mnemonic.

With the option --relaxed the assembler accepts 2-operand versions of 3-operand instructions when the first and second operand are a destination and a source register and the same register is used for both, e.g. 'add r1,r1,r3' may be written as 'add r1,r3' and 'add r1,r1,#4' may be written as 'add r1,#4'.

Before v1.1r4, the assembler did not accept that both registers were specified for double-word memory access instructions. An instruction pair could only be specified by its even register.

You should not add 1 to Thumb label expressions in literal pools or data sections. This will be taken care of automatically by the assembler and the linker.

EABI issues

Before v1.1r4, the assembler and the linker did not emit mapping symbols ($a, $d and $t) to mark address ranges containing ARM code, data or Thumb code respectively. This implies that before v1.1r4 in some situations the debugger does not correctly disassemble the code.


The linker automatically generates ARM-Thumb interworking veneers when needed. This release always creates a long veneer, i.e. short veneers and inline veneers are not used. Veneer symbol names do not follow the convention proposed by the EABI (not mandatory).

The linker does not generate long-branch veneers for out-of-range function calls by default. You can enabled this feature with option --long-branch-veneers, but use it with care. The option slows down the linking process considerably and it can lead to larger code size even when veneers are not needed after all. It is better to prevent long branches and only use this option when long branches are out of range.

New linker options (since version 1.2r1)

 Option Description
--import-object=<file>,... With this option the linker will import a binary file containing raw data and place it in a section. The section name is derived from the filename, in which dots are replaced by an underscore. So when importing a file called my.jpg, a section with the name my_jpg is created. In your application you can refer to the created section by using linker labels.


All product libraries are compiled for ARM-Thumb interworking.

The startup code for ARM and Thumb (cstart.asm) included in the C library (carm.lib & cthumb.lib) provides basic functionality: it initializes the separate stack pointers for each processor mode, copies global data from ROM to RAM, calls the application's main function and calls the exit function upon return from main. It does not do any hardware initialization. You may contact Altium Support for assistance on hardware-specific issues pertaining to the use of the TASKING VX-toolset.

Run-time library (since version 1.1r2)

Since version 1.1r2 the compiler related functions are removed from the C library and put into a separated run-time library (rtarm.lib & rtthumb.lib).

Third party libraries (since version 1.1r3 & 1.1r4)

Since version 1.1r3 the following third party libraries (and header files) are included:

Library Description
str71xstdlibarm.lib STMicroelectronics STR71x Software Library (ARM)
str71xstdlibthumb.lib STMicroelectronics STR71x Software Library (Thumb)
str73xstdlibarm.lib STMicroelectronics STR73x Software Library (ARM)
str73xstdlibthumb.lib STMicroelectronics STR73x Software Library (Thumb)
str91xstdlibarm.lib STMicroelectronics STR91x Software Library (ARM)
str91xstdlibthumb.lib STMicroelectronics STR91x Software Library (Thumb)

Since version 1.1r4 the following third party libraries (and header files) are included:

Library Description
str75xstdlibarm.lib STMicroelectronics STR75x Software Library (ARM)
str75xstdlibthumb.lib STMicroelectronics STR75x Software Library (Thumb)

FSS version 2 (since version 1.1r4)

The library contains a more general debugger call interface including file system simulation 2.


The CrossView Pro instruction set simulator debugger is part of this release.

The debugger recognizes register alias names IP, SP, LR and PC for general purpose registers R12, R13, R14 and R15. You can display these aliases in the register window. The disassembler only shows the general purpose names.

Initialize CPSR & SPSR_xxx registers after an application or system reset (since version 1.1r4)

Since version 1.1r4 CrossView Pro sets the value of the CPSR register to 0xd3 and SPSR_xxx to 0x10 on a application or system reset. This ensures a correct rerun of a Thumb application.


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