This appendix contains the following sections:
Introduction
CPU Functional Problem Bypasses TC1 V1.2
TC112_COR1
TC112_COR3
TC112_COR4
TC112_COR6
TC112_COR10
TC112_COR13
TC112_COR14
TC112_COR15
TC112_COR16
TC112_COR17
CPU Functional Problem Bypasses TC1 V1.3
TC113_PMU1
TC113_PMU3
TC113_CPU5
TC113_CPU9
TC113_CPU11
TC113_CPU13
TC113_CPU14
TC113_CPU15
TC113_CPU16
TC113_DMU1
TC113_LF12
TC113_LF13
Infineon Technologies regularly publishes microcontroller errata sheets reporting functional problems and deviations from the electrical specifications and timing specifications.
The TASKING TriCore software development tools provide solutions for a number of these functional problems in the TriCore architecture.
Support to deal with CPU functional problem is provided in three areas:
This appendix lists a summary of identified functional problems which can be bypassed by the TASKING TriCore tool kit.
Please refer to the Infineon errata sheets for the TriCore architecture revision-step of your particular device, to check the need for applying any of these bypasses. Also refer to the Infineon errata sheets for a complete description of the CPU functional problems, as the workarounds listed below do not describe the functional problem itself.
The syntax used by Infineon to identify a CPU functional problems is:
For example: TC113_CPU5 (TC1, version 1.3, module "CPU", problem #5)
With the TASKING C compiler and assembler command line options, pragmas and macro definitions you can enable or disable specific CPU functional problem bypasses.
To enable the compiler bypasses and assembler checks for all TriCore CPU TC112 problems (respectively TC113 problems) at once, use the command line option -zTC112_DEFECTS or #pragma TC112_DEFECTS (respectively -zTC113_DEFECTS or #pragma TC113_DEFECTS)
In the embedded development environment (EDE) you can enable as follows:
Select the EDE | Processor Options... menu and chooose the Bypasses TC1 v1.2 tab or the Bypasses TC1 v1.3 tab. Then select the bypasses you want to enable.
The table below shows an overview of all CPU functional problems.
TC Version | Functional Problem |
112 | COR1 |
112 | COR3 |
112 | COR4 |
112 | COR6 |
112 | COR10 |
112 | COR13 |
112 | COR14 |
112 | COR15 |
112 | COR16 |
112 | COR17 |
113 | PMU1 |
113 | PMU3 |
113 | CPU5 |
113 | CPU9 |
113 | CPU11 |
113 | CPU13 |
113 | CPU14 |
113 | CPU15 |
113 | CPU16 |
113 | DMU1 |
113 | LFI2 |
113 | LFI3 |
Table C-1: Overview of supported TriCore CPU functional problems
-zTC112_COR1
#pragma TC112_COR1 [on|off|restore]
$TC112_COR1 {on|off}
The assembler macro _TC112_COR1 is defined if you specify the option -zTC112_COR1.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates an ISYNC instruction before each LOOP, LOOP16 and LOOPU instruction.
The assembler gives a warning when the preceding instruction of a LOOP, LOOP16 or LOOPU instruction is not an ISYNC instruction:
171 suspicious instruction concerning CPU functional defect TC112_COR1
You can suppress this warning with the option -w171.
To bypass this CPU functional problem, a locator control is used in the tri.cpu descriptor to restrict the size in the CSA absolute address mapping to 32Kb scratch pad RAM on the DMU.
The assembler macro _TC112_COR4 is defined if you specify the option -zTC112_COR4.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between a (target) label and the instruction following it This is done when the instruction directly uses an An register for either an effective address calculation or as the target of an indirect branch.
The assembler gives a warning for an instruction using an An register for either an effective address calculation or as the target of an indirect branch that is located directly after a (target) label:
172 suspicious instruction concerning CPU functional defect TC112_COR4
You can suppress this warning with the option -w172.
The assembler macro _TC112_COR6 is defined if you specify the option -zTC112_COR6.
lib\p\tc112\*.a
There is no C compiler workaround required for this CPU functional problem, because the compiler does not generate CALLI instructions with a target address in register A11.
The assembler generates an error for instruction CALLI A11.
-zTC112_COR10
#pragma TC112_COR10 [on|off|restore]
$TC112_COR10 {on|off}
The assembler macro _TC112_COR10 is defined if you specify the option -zTC112_COR10.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler avoids generation of store instructions that use a circular addressing mode with an offset value not equal to zero. An additional circular load instruction is generated with the required offset to post-increment the circular buffer pointer.
For example:
st.w [a6/a7+c]0,d15 ld.w d15,[a6/a7+c]4
Instead of:
st.w [a6/a7+c]4,d15
The assembler gives a warning for store operations that use a circular addressing mode with an offset not equal to zero:
173 suspicious instruction concerning CPU functional defect TC112_COR10
You can suppress this warning with the option -w173.
-zTC112_COR13
#pragma TC112_COR13 [on|off|restore]
$TC112_COR13 {on|off}
The assembler macro _TC112_COR13 is defined if you specify option -zTC112_COR13.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP prior to the LOOP instruction if the loop contains a single integer instruction that is a DVSTEP or a DVSTEP.U.
The assembler gives a warning for loops that contain a single integer instruction that is a DVSTEP or a DVSTEP.U:
174 suspicious instruction concerning CPU functional defect TC112_COR13
You can suppress this warning with the option -w174.
-zTC112_COR14
#pragma TC112_COR14 [on|off|restore]
$TC112_COR14 {on|off}
The assembler macro _TC112_COR14 is defined if you specify the option -zTC112_COR14.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler uses code that protects a divide instruction sequence against interrupts. Instead of generating inline divide code, the C compiler generates calls to run-time library functions that support divide operations with interrupt protection. Next skeleton code demonstrates the protective code used in these run-time library functions:
;; ;; Save interrupt state and disable interrupts ;; mfcr d0,#0xfe2c ; save ICR in d0 disable ; disable interrupts
divide instructions:
;; ;; Restore interrupt state ;; jz.t d0:8,disabled ; do not enable interrupts enable ; when they were disabled disabled:
The C run-time library modules involved are acircint.asm, dfrfr.asm, sdivmod.asm and udivmod.asm.
An assembler check for this CPU functional problem is not available, because global interrupt enable state can not be checked at assembly level.
-zTC112_COR15
$TC112_COR15 {on|off}
The assembler macro _TC112_COR15 is if you specify the option -zTC112_COR15.
lib\p\tc112\*.a (or add lib\src\cstart.asm to your project).
To bypass this CPU functional problem, an assembler macro is added to the C startup code to disable the starvation protection by resetting the BCUCON.SPE bit.
No assembler check is supported, because run time checking of starvation protection is not possible at assembly level.
-zTC112_COR16
-em_TC112_COR16
#pragma TC112_COR16 [on|off|restore]
$TC112_COR16 {on|off}
The assembler macro _TC112_COR16 is defined if you specify the option -zTC112_COR16.
lib\p\tc112\*.a (or add lib\src\cstart.asm to your project).
To bypass this CPU functional problem, the C compiler aligns circular qualified buffers to a quad-word boundary, and the compiler sizes all stack frames to an integral number of quad-words. An assembler macro isadded to the C startup code to enable initialization of the stack pointers to a quad-word boundary. A locator control is used in the tri.dsc descriptor to set the alignment of the user stack and the interrupt stack to a quad-word alignment. See section 3.20 , Circular Buffers for a description on how to declare a circular buffer.
No assembler check is supported, because circular storage type info is not available at assembly level.
-zTC112_COR17
#pragma TC112_COR17 [on|off|restore]
$TC112_COR17 {on|off}
The assembler macro _TC112_COR17 is defined if you specify the option -zTC112_COR17.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction after a DSYNC instruction. The C compiler only generates a DSYNC instruction when bypass TC113_CPU17 is enabled.
The assembler gives a warning if a DSYNC is not followed by a NOP instruction:
175 suspicious instruction concerning CPU functional defect TC112_COR17
You can suppress this warning with the option -w175.
-zTC113_PMU1
lib\p\tc113\*.a, or add lib\src\cstart.asm to your project.
The assembler macro _TC113_PMU1 is defined if you specify the option -zTC113_PMU1.
To bypass this CPU functional problem, an assembler macro is added to the C startup code to disable the split mode on the LMB bus. The SPLT bit of the SFR register LFI_CON is set to zero.
No assembler check is supported, because run time split mode can not
be
checked at assembly level.
-zTC113_PMU3
The assembler macro _TC113_PMU3 is defined if you specify the option -zTC113_PMU3.
lib\p\tc113\*.a (or add lib\src\cstart.asm to your project).
To bypass this CPU functional problem, an assembler macro is added to the C startup code to set the TLB-A and TLB-B mappings to a page size of 16 Kb. The SZA and SZB in the MMU_CON are set to 16 Kb.
No assembler check is supported, because run time TBL mappings can not be checked at assembly level.
-zTC113_CPU5
#pragma TC113_CPU5 [on|off|restore]
$TC113_CPU5 {on|off}
The assembler macro _TC113_CPU5 is defined if you specify the option -zTC113_CPU5.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates an ISYNC instruction before a loop body.
Example:
isync _loop_start: .. .. loop a8, _loop_start
This CPU functional problem does not cause a run-time problem, it is only a performance issue. Therefor no assembler checking is required to warn you for possible run-time problems.
-zTC113_CPU9
#pragma TC113_CPU9 [on|off|restore]
$TC113_CPU9 {on|off}
The assembler macro _TC113_CPU9 is defined if you specify the option -zTC113_CPU9.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates two NOP instructions after a DSYNC instruction. The C compiler only generates a DSYNC instruction when CPU functional problem bypass TC113_CPU14 is enabled.
The assembler gives a warning if a DSYNC is not followed by two NOP instructions:
176 suspicious instruction concerning CPU functional defect TC113_CPU9
You can suppress this warning with the option -w176.
-zTC113_CPU11
#pragma TC113_CPU11 [on|off|restore]
$TC113_CPU11 {on|off}
The assembler macro _TC113_CPU11 is defined if you specify the option -zTC113_CPU11.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between a LDA, LDDA, LD16A and the JI instruction. The compiler also generates a NOP before a RET and RET16 instruction if there is no or just one instruction before RET, starting from the function entry point.
The assembler gives a warning when an LDA, LDDA, or LD16A instruction is directly followed by a JI instruction. The assembler also gives a warning when there is no or just one instruction (not a NOP instruction) between label and RET or RET16:
177 suspicious instruction concerning CPU functional defect TC113_CPU11
You can suppress this warning with the option -w177.
-zTC113_CPU13
The assembler macro _TC113_CPU13 is defined if you specify the option -zTC113_CPU13.
lib\p\tc113\*.a (or add lib\src\cstart.asm to your project).
To bypass this CPU functional problem, an assembler macro is added to the C startup code to enable the 16Kb D-Cache. The DCSIZ bits are set to 16Kb in the SFR register DMU_CON.
No assembler check is supported, because run time D-Cache size can not be checked at assembly level. As an alternative, you can use the TC113_CPU14 assembler check and workaround. You can also insert a DSYNC to workaround this CPU functional problem.
-zTC113_CPU14
#pragma TC113_CPU14 [on|off|restore]
$TC113_CPU14 {on|off}
The assembler macro _TC113_CPU14 is defined if you specify the option -zTC113_CPU14.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a DSYNC instruction directly after a (interrupt) function entry point label. Also an assembler macro is added to the run-time library functions for optionally adding a DSYNC instruction after a function entry point label.
The assembler gives a warning when the first label in a code section is not followed by a DSYNC instruction:
178 suspicious instruction concerning CPU functional defect TC113_CPU14
You can suppress this warning with the option -w178.
-zTC113_CPU15
#pragma TC113_CPU15 [on|off|restore]
$TC113_CPU15 {on|off}
The assembler macro _TC113_CPU15 is defined if you specify the option -zTC113_CPU15.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of the ST.T, SWAP and LDMST instructions. For immediate _bit and bit-field operations alternative instructions are used.
The assembler gives a warning for ST.T, SWAP and LDMST instructions:
179 suspicious instruction concerning CPU functional defect TC113_CPU15
You can suppress this warning with the option -w179.
-zTC113_CPU16
#pragma TC113_CPU16 [on|off|restore]
$TC113_CPU16 {on|off}
The assembler macro _TC113_CPU16 is defined if you specify the option -zTC113_CPU16.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between an LDA, LDDA, LD16A and the JI or CALLI instruction with the same address register as parameter. The compiler also generates a NOP instruction before a RET and RET16 instruction if there is no or just one instruction before RET, starting from the function entry point.
The assembler gives a warning when an LDA, LDDA or LD16A instruction is directly followed by a JI or CALLI instruction with the same address register as parameter. The assembler also gives a warning when there is no or just one instruction (not a NOP instruction) between label and RET or RET16:
180 suspicious instruction concerning CPU functional defect TC113_CPU16
You can suppress this warning with the option -w180.
-zTC113_DMU1
#pragma TC113_DMU1 [on|off|restore]
$TC113_DMU1 {on|off}
The assembler macro _TC113_DMU1 is defined if you specify the option -zTC113_DMU1.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of the ST.T, SWAP and LDMST instructions. For direct _bit and bit-field operations, alternative instructions are used.
The assembler gives a for SWAP, LDMST and ST.T instructions:
181 suspicious instruction concerning CPU functional defect TC113_DMU1
You can suppress this warning with the option -w181.
-zTC113_LFI2
#pragma TC113_LFI2 [on|off|restore]
$TC113_LFI2 {on|off}
The assembler macro _TC113_LFI2 is defined if you specify the option -zTC113_LFI2.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of ST.T, SWAP and LDMST instructions. For immediate _bit and bit-field operations alternative instructions are used.
The assembler gives a warning for SWAP, LDMST and ST.T instructions:
182 suspicious instruction concerning CPU functional defect TC113_LFI2
You can suppress this warning with the option -w182.
-zTC113_LFI3
#pragma TC113_LFI3 [on|off|restore]
$TC113_LFI3 {on|off}
The assembler macro _TC113_LFI3 is defined if you specify the option -zTC113_LFI3.
lib\p\tc113\*.a
To bypass this CPU functional problem, the compiler avoids generation of the ST.T, SWAP and LDMST instructions. For direct _bit and bit-field operations alternative instructions are used.
The assembler gives a warning for SWAP, LDMST and ST.T instructions:
183 suspicious instruction concerning CPU functional defect TC113_LFI3
You can suppress this warning with the option -w183.