ON-CHIP DEBUG SUPPORT

This addendum contains the following sections:

Introduction

Supported Hardware

Additional System Requirements

Restrictions

Configuring CrossView Pro

Infineon Board OCDS Interface Circuit
The Infineon JTAG Connector
The Connector Layout
Implementation Considerations

1 Introduction

This addendum gives supporting information for use of CrossView Pro with the on-chip debug support (OCDS) of the TriCore micro-controller (MCU) family. Part of the OCDS concept is the JTAG debug connection, an industry standard serial connection with the MCU's inner states. OCDS allows pervasive debugging control of the MCU.

2 Supported Hardware

CrossView Pro supports the following hardware:

All of the boards use the OCDS interface integrated on the board.

3 Additional System Requirements

The following are the additional system requirements:

4 Restrictions

Facilities for background mode are absent for the TriCore target boards. As a consequence, the CrossView Pro commands CB, st, u, ubgw and wt for background mode, are not available. Due to the binary command interface between the debugger and the target board, the >& command to record target communication and the o command for transparency mode are not available. Command line function calls are not supported. Also Coverage and Profiling are not supported. As a consequence, the CrossView Pro commands ce, cd, covinfo, pe, pd, proinfo, cproinfo, nC, nU, pC, and pU are not available.

Menu and dialog items related to the mentioned commands are disabled (grayed out).

5 Configuring CrossView Pro

In CrossView Pro choose one of the OCDS target configurations, reachable via Project | CrossView Pro Options | Execution. Select "Target Board via OCDS" and choose a Target Board.

6 Infineon Board OCDS Interface Circuit

To enable JTAG debugging with a custom target board, you can add the Infineon OCDS interface circuit to it. This circuit in effect only serves to protect the microcontroller from voltage peaks and operates as a voltage level shifter if necessary.

Halting the target also implies that servicing interrupts is inhibited.

Figure OCDS-1: Infineon OCDS Interface Electric Schematics

Number of parts Part
2 74HC244
9 10k Ohm
1 470 Ohm
1 110 Ohm
2 51 Ohm
7 82 Ohm
1 1 nF
1 10 nF
1 LED
1 DB25 Female connector

Table OCDS-1: Parts list

6.1 The Infineon JTAG connector

Since there is no standard connector defined in the IEEE1149.1 JTAG standard specification nor an established industry standard has emerged, Infineon has defined their own standard connector for debugging purposes.

6.1.1 The connector Layout

Mechanical

The connector is a standard 2.54mm (0.1 inch) centers.

Figure OCDS-2: Infineon JTAG Connector V1.2

Signal description

Table OCDS-2 contains the Infineon JTAG connector signals. The direction is specified as follows:

O = output from the CPU processor board to the debugger

I = input to the CPU processor board from the debugger

Signal Name Direction Pin Number Comment
TDO O 3 IEEE 1149.1
TDI I 7 IEEE 1149.1
TMS I 1 IEEE 1149.1
TCLK I 11 IEEE 1149.1
TRST I 9 IEEE 1149.1
Brk_IN I 13
Brk_OUT O 10
RESET I 8 Open collector
CPU_CLOCK O 5 Optional
TRAP O 15 TriCore only
OCDS_E I 14 TriCore only. Must be held down during reset
GND - 4,6,12
VCC O 2 I/O ring voltage of CPU
Key I 16 Mechanical key, should be driven to GND by the debugger.

Table OCDS-2: Signal names of the JTAG connector

Voltage

All signals have the voltage of the I/O ring. The current voltages are 5 Volt, 3.3 Volt or 2 Volt VCC.

Frequencies

The speed of the JTAG signals must not exceed 200% of the actual CPU clock speed.

6.1.2 Implementation Considerations

Pull Up's & Down's

The following signals should be connected to pull-up's or pull-down's respectively on the CPU-board.

Signals Pull-up Pull-down
OCDS_E 10k
TMS 10k
TDI 10k
TRST 10k
RESET 10k
Brk_IN 10k
TCLK 10k

Table OCDS-3: Pull-up's & Down's

Clock Pin

The clock is optional since not every CPU has a Clock-out pin available. Since the clock pin is very likely to act as a antenna, it should be connected via any sort of Jumper.

If not applied, the TCLK signal should be connected to GND to enable sensing of the clock signal's presence.

Mechanical Key Pin (no Pin)

The key pin signal should be driven by the debugger side to GND.

OCDS_E Pin

This pin has to be held down during RESET to enable OCDS. (TriCore only)


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