This chapter contains the following sections:
CPU Functional Problem Bypasses TC1 V1.2
TC112_COR1
TC112_COR3
TC112_COR4
TC112_COR6
TC112_COR7
TC112_COR10
TC112_COR13
TC112_COR14
TC112_COR15
TC112_COR16
TC112_COR17
CPU Functional Problem Bypasses TC1 V1.3
TC113_CPU5
TC113_CPU9
TC113_CPU11
TC113_CPU13
TC113_CPU14
TC113_CPU15
TC113_CPU16
TC113_DMU1
TC113_LF12
TC113_LF13
TC113_PMU1
TC113_PMU3
Infineon Technologies regularly publishes microcontroller errata sheets reporting functional problems and deviations from the electrical specifications and timing specifications.
The TASKING TriCore software development tools provide solutions for a number of these functional problems in the TriCore architecture.
Support to deal with CPU functional problem is provided in three areas:
This chapters lists a summary of identified functional problems which can be bypassed by the TASKING TriCore tool kit.
Please refer to the Infineon errata sheets for the TriCore architecture revision-step of your particular device, to check the need for applying any of these bypasses. Also refer to the Infineon errata sheets for a complete description of the CPU functional problems, as the workarounds listed below do not describe the functional problem itself.
The syntax used by Infineon to identify a CPU functional problems is:
For example: TC113_CPU5 (TC1, version 1.3, module "CPU", problem #5)
With the TASKING C compiler and assembler command line options, pragmas and macro definitions you can enable or disable specific CPU functional problem bypasses.
To enable the compiler bypasses and assembler checks for all TriCore CPU TC112 problems (respectively TC113 problems) at once, use the command line option --silicon-bug=all-tc112 (respectively --silicon-bug=all-tc113)
To enable the bypasses from the embedded development environment (EDE):
1. From the Projects menu select Project Options...
2. Expand the Processor entry
3. Select Bypasses. Depending on the target processor you have selected, this shows the bypasses for the TC1 v1.2 or TC1 v1.3.
The table below shows an overview of all CPU functional problems.
TC Version | Functional Problem |
112 | COR1 |
112 | COR3 |
112 | COR4 |
112 | COR6 |
112 | COR7 |
112 | COR10 |
112 | COR13 |
112 | COR14 |
112 | COR15 |
112 | COR16 |
112 | COR17 |
113 | CPU5 |
113 | CPU9 |
113 | CPU11 |
113 | CPU13 |
113 | CPU14 |
113 | CPU15 |
113 | CPU16 |
113 | DMU1 |
113 | LFI2 |
113 | LFI3 |
113 | PMU1 |
113 | PMU3 |
Table A-2: Overview of supported TriCore CPU functional problems
--silicon-bug=cor1
$TC112_COR1 {on|off}
The assembler macro __TC112_COR1__ is defined if you specify the option --silicon-bug=cor1.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates an ISYNC instruction before each LOOP, LOOP16 and LOOPU instruction.
The assembler gives a warning when the preceding instruction of a LOOP, LOOP16 or LOOPU instruction is not an ISYNC instruction:
W253: suspicious instruction concerning CPU functional defect TC112_COR1
You can suppress this warning with the option -w253.
To bypass this CPU functional problem, a preprocessor define is used in the tc*.lsl linker script files to restrict the size in the CSA absolute address mapping to 32Kb scratch pad RAM on the DMU.
The assembler macro __TC112_COR4__ is defined if you specify the option --silicon-bug=cor4.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between a (target) label and the instruction following it This is done when the instruction directly uses an An register for either an effective address calculation or as the target of an indirect branch.
The assembler gives a warning for an instruction using an An register for either an effective address calculation or as the target of an indirect branch that is located directly after a (target) label:
W254: suspicious instruction concerning CPU functional defect TC112_COR4
You can suppress this warning with the option -w254.
The assembler macro __TC112_COR6__ is defined if you specify the option --silicon-bug=cor6.
lib\p\tc112\*.a
There is no C compiler workaround required for this CPU functional problem, because the compiler does not generate CALLI instructions with a target address in register A11.
The assembler generates an error for instruction CALLI A11.
The assembler macro __TC112_COR7__ is defined if you specify the option --silicon-bug=cor7.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction at the very top of any subroutine if it was previously beginning with a CALL instruction and in a "multiple DMU master" situation.
The assembler gives a warning when the register A11 is incorrectly updated if there is a status "DMU not ready" on the second micro op of a 2 cycle call variant. This is due to an error in the fetch unit block.
W255: suspicious instruction concerning CPU functional defect TC112_COR7
You can suppress this warning with the option -w255.
--silicon-bug=cor10
$TC112_COR10 {on|off}
The assembler macro __TC112_COR10__ is defined if you specify the option --silicon-bug=cor10.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler avoids generation of store instructions that use a circular addressing mode with an offset value not equal to zero. An additional circular load instruction is generated with the required offset to post-increment the circular buffer pointer.
For example:
st.w [a6/a7+c]0,d15 ld.w d15,[a6/a7+c]4
Instead of:
st.w [a6/a7+c]4,d15
The assembler gives a warning for store operations that use a circular addressing mode with an offset not equal to zero:
W256: suspicious instruction concerning CPU functional defect TC112_COR10
You can suppress this warning with the option -w256.
--silicon-bug=cor13
$TC112_COR13 {on|off}
The assembler macro __TC112_COR13__ is defined if you specify option --silicon-bug=cor13.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP prior to the LOOP instruction if the loop contains a single integer instruction that is a DVSTEP or a DVSTEP.U.
The assembler gives a warning for loops that contain a single integer instruction that is a DVSTEP or a DVSTEP.U:
W257: suspicious instruction concerning CPU functional defect TC112_COR13
You can suppress this warning with the option -w257.
--silicon-bug=cor14
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler uses code that protects a divide instruction sequence against interrupts. Instead of generating inline divide code, the C compiler generates calls to run-time library functions that support divide operations with interrupt protection. Next skeleton code demonstrates the protective code used in these run-time library functions:
;; ;; Save interrupt state and disable interrupts ;; mfcr d0,#0xfe2c ; save ICR in d0 disable ; disable interrupts
divide instructions:
;; ;; Restore interrupt state ;; jz.t d0:8,disabled ; do not enable interrupts enable ; when they were disabled disabled:
The C run-time library modules involved are acircint.asm, dfrfr.asm, sdivmod.asm and udivmod.asm.
An assembler check for this CPU functional problem is not available, because global interrupt enable state cannot be checked at assembly level.
--silicon-bug=cor15
$TC112_COR15 {on|off}
The assembler macro __TC112_COR15__ is if you specify the option --silicon-bug=cor15.
lib\p\tc112\*.a (or add lib\src\cstart.asm to your project).
There is no compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to disable the starvation protection by resetting the BCUCON.SPE bit.
--silicon-bug=cor16
-D__TC112_COR16__
$TC112_COR16 {on|off}
The assembler macro __TC112_COR16__ is defined if you specify the option --silicon-bug=cor16.
lib\p\tc112\*.a (or add lib\src\cstart.asm to your project).
To bypass this CPU functional problem, the C compiler aligns circular qualified buffers to a quad-word boundary, and the compiler sizes all stack frames to an integral number of quad-words. See section 3.4.1, Circular Buffers in the User's Guide, for a description on how to declare a circular buffer.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to enable initialization of the stack pointers to a quad-word boundary.
A preprocessor define is used in the tc*.lsl linker script files to set the alignment of the user stack and the interrupt stack to a quad-word alignment.
--silicon-bug=cor17
$TC112_COR17 {on|off}
The assembler macro __TC112_COR17__ is defined if you specify the option --silicon-bug=cor17.
lib\p\tc112\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction after a DSYNC instruction. The C compiler only generates a DSYNC instruction when bypass TC113_CPU17 is enabled.
The assembler gives a warning if a DSYNC is not followed by a NOP instruction:
W258: suspicious instruction concerning CPU functional defect TC112_COR17
You can suppress this warning with the option -w258.
--silicon-bug=cpu5
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates an ISYNC instruction before a loop body.
Example:
isync _loop_start: .. .. loop a8, _loop_start
This CPU functional problem does not cause a run-time problem, it is only a performance issue. Therefor no assembler checking is required to warn you for possible run-time problems.
--silicon-bug=cpu9
$TC113_CPU9 {on|off}
The assembler macro __TC113_CPU9__ is defined if you specify the option --silicon-bug=cpu9.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates two NOP instructions after a DSYNC instruction. The C compiler only generates a DSYNC instruction when CPU functional problem bypass TC113_CPU14 is enabled.
The assembler gives a warning if a DSYNC is not followed by two NOP instructions:
W259: suspicious instruction concerning CPU functional defect TC113_CPU9
You can suppress this warning with the option -w259.
--silicon-bug=cpu11
#pragma TC113_CPU11 [on|off|restore]
$TC113_CPU11 {on|off}
The assembler macro __TC113_CPU11__ is defined if you specify the option --silicon-bug=cpu11.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between a LDA, LDDA, LD16A and the JI instruction. The compiler also generates a NOP before a RET and RET16 instruction if there is no or just one instruction before RET, starting from the function entry point.
The assembler gives a warning when an LDA, LDDA, or LD16A instruction is directly followed by a JI instruction. The assembler also gives a warning when there is no or just one instruction (not a NOP instruction) between label and RET or RET16:
W260: suspicious instruction concerning CPU functional defect TC113_CPU11
You can suppress this warning with the option -w260.
--silicon-bug=cpu13
The assembler macro __TC113_CPU13__ is defined if you specify the option --silicon-bug=cpu13.
lib\p\tc113\*.a (or add lib\src\cstart.asm to your project).
There is no compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to enable the 16Kb D-Cache. The DCSIZ bits are set to 16Kb in the SFR register DMU_CON.
--silicon-bug=cpu14
$TC113_CPU14 {on|off}
The assembler macro __TC113_CPU14__ is defined if you specify the option --silicon-bug=cpu14.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a DSYNC instruction directly after a (interrupt) function entry point label. Also an assembler macro is added to the run-time library functions for optionally adding a DSYNC instruction after a function entry point label.
The assembler gives a warning when the first label in a code section is not followed by a DSYNC instruction:
W261: suspicious instruction concerning CPU functional defect TC113_CPU14
You can suppress this warning with the option -w261.
--silicon-bug=cpu15
$TC113_CPU15 {on|off}
The assembler macro __TC113_CPU15__ is defined if you specify the option --silicon-bug=cpu15.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of the ST.T, SWAP and LDMST instructions. For immediate __bit and bit-field operations alternative instructions are used.
The assembler gives a warning for ST.T, SWAP and LDMST instructions:
W262: suspicious instruction concerning CPU functional defect TC113_CPU15
You can suppress this warning with the option -w262.
--silicon-bug=cpu16
$TC113_CPU16 {on|off}
The assembler macro __TC113_CPU16__ is defined if you specify the option --silicon-bug=cpu16.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler generates a NOP instruction between an LDA, LDDA, LD16A and the JI or CALLI instruction with the same address register as parameter. The compiler also generates a NOP instruction before a RET and RET16 instruction if there is no or just one instruction before RET, starting from the function entry point.
The assembler gives a warning when an LDA, LDDA or LD16A instruction is directly followed by a JI or CALLI instruction with the same address register as parameter. The assembler also gives a warning when there is no or just one instruction (not a NOP instruction) between label and RET or RET16:
W263: suspicious instruction concerning CPU functional defect TC113_CPU16
You can suppress this warning with the option -w263.
--silicon-bug=dmu1
$TC113_DMU1 {on|off}
The assembler macro __TC113_DMU1__ is defined if you specify the option --silicon-bug=dmu1.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of the ST.T, SWAP and LDMST instructions. For direct __bit and bit-field operations, alternative instructions are used.
The assembler gives a for SWAP, LDMST and ST.T instructions:
W264: suspicious instruction concerning CPU functional defect TC113_DMU1
You can suppress this warning with the option -w264.
--silicon-bug=lfi2
$TC113_LFI2 {on|off}
The assembler macro __TC113_LFI2__ is defined if you specify the option --silicon-bug=lfi2.
lib\p\tc113\*.a
To bypass this CPU functional problem, the C compiler avoids generation of ST.T, SWAP and LDMST instructions. For immediate __bit and bit-field operations alternative instructions are used.
The assembler gives a warning for SWAP, LDMST and ST.T instructions:
W265: suspicious instruction concerning CPU functional defect TC113_LFI2
You can suppress this warning with the option -w265.
--silicon-bug=lfi3
$TC113_LFI3 {on|off}
The assembler macro __TC113_LFI3__ is defined if you specify the option --silicon-bug=lfi3.
lib\p\tc113\*.a
To bypass this CPU functional problem, the compiler avoids generation of the ST.T, SWAP and LDMST instructions. For direct __bit and bit-field operations alternative instructions are used.
The assembler gives a warning for SWAP, LDMST and ST.T instructions:
W266: suspicious instruction concerning CPU functional defect TC113_LFI3
You can suppress this warning with the option -w266.
--silicon-bug=pmu1
lib\p\tc113\*.a, or add lib\src\cstart.asm to your project.
The assembler macro __TC113_PMU1__ is defined if you specify the option --silicon-bug=pmu1.
There is no compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to disable the split mode on the LMB bus. The SPLT bit of the SFR register LFI_CON is set to zero.
--silicon-bug=pmu3
The assembler macro __TC113_PMU3__ is defined if you specify the option --silicon-bug=pmu3.
lib\p\tc113\*.a (or add lib\src\cstart.asm to your project).
There is no compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to set the TLB-A and TLB-B mappings to a page size of 16 Kb. The SZA and SZB in the MMU_CON are set to 16 Kb.