This appendix contains the following sections:
Introduction
Fixed Register Set
CrossView Pro has a user definable set of special function registers (SFRs). The set of SFR's can vary with the CPU type. The registers are read by CrossView Pro from a file (regcpu.def) specified by the cpu_type field in xvw.ini. You can overrule the CPU type (and thus the regcpu.def file) to be used by CrossView Pro by specifying another CPU type in the Target | Settings dialog or with the -C command line option.
The register definition file contains the register name to address mapping. Register definition files for TriCore derivatives are included in the package and are actually identical to the assembler SFR include files. If you use another derivative you can use any text editor to create new register definition files.
In addition to the registers defined in the register definition file CrossView Pro uses a fixed set of additional registers for the TriCore, these are defined in the section Fixed Register Set. The mapping for these registers is done by the execution environment.
The following registers are always defined.
Register |
A0 ... A15 |
D0 ... D15 |
PC |
PSW |
PCXI |
CCNT |
CBRK |
Table C-1: Fixed Register Set
A0 .. A15 The standard TriCore address registers.
D0 .. D15 The standard TriCore data registers.
PC The program counter.
PSW The program status word.
PCXI The previous context information register.
CCNT The CycleCouNT register. The number of execution cycles is recorded in the CCNT register. The cyclecount register is not an on-chip register, nor a memory location on the target system, but an CrossView Pro internal data structure that can be accessed as if it is an ordinary register. The CCNT register is 32 bits wide.
CBRK The CycleBReaK register. The cyclebreak register is an CrossView Pro internal data structure that can be accessed as if it is an ordinary register. The CBRK register is used in combination with the CCNT register to set a breakpoint on the number of processor cycles consumed by your application. If the number of processor cycles used is greater than the value stored in the CBRK register a "cycle counter breakpoint" is generated and execution is suspended. When CBRK is set to 0xffffffff cycle counter breakpoints are suppressed. The CBRK register is 32 bits wide.