This release note describes the changes and new features of all TASKING TriCore products since v2.5r2. This patch contains some bug-fixes for the C Compiler.
The following parts are described:
The main reasons for this release are:
For the description for this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
Whenever
an mtcr is generated, which is not preceded by a dsync, the compiler
will give warning W755
"Due to functional defect CPU_TC.105 the use of the mtcr instruction is
not recommended": Under
some conditions the use of mtcr leads to errors (see Errata Sheet), a
dsync before the mtcr prevents these problems, but is in most
situations not necessary.
To enable this warning, the option --silicon-bug=cpu-tc105
must be
specified on command line.
For the description of this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
Whenever an
mtcr is generated, preceded by a mul, madd, msub or rstv, the compiler
will give warning W756
"Due to functional defect CPU_TC.106 the use of the mtcr instruction is
not recommended": Under
some conditions the use of mtcr directly after a mul/madd/msub/rstv
instruction leads to errors (see Errata Sheet), a nop before the mtcr
prevents these problems, but is in most situations not necessary.
To enable this warning, the option --silicon-bug=cpu-tc106
must be
specified on command line.
For the description for this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
The compiler inserts a nop
before a load
or store instruction using a circular addressing mode.
To enable this workaround, the option --silicon-bug=cpu-tc108
must be
specified on command line.
For the description for this deviation see "Errata Sheet TC1767ED AD, v1.0 dd 2008-07-04".
Whenever a load word
instruction, using circular addressing
mode, is preceded by a store byte instruction, or when only a single
ip-instruction is in between such a load word instruction and a store
byte instruction, the compiler inserts a nop before the load word
instruction.
To enable this workaround, the option --silicon-bug=cpu-tc109
must be
specified on command line.
For the description for this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
Whenever an mtcr is
encountered, which is not preceded by a dsync, the assembler
will give warning W827
"suspicious
instruction concerning CPU functional defect CPU_TC.105".
To enable this warning, the option --silicon-bug=cpu-tc105
must be
specified on command line.
For the description of this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
Whenever an
mtcr is encountered, preceded by a mul, madd, msub or rstv, the
assmebler
will give warning W828
"suspicious
instruction concerning CPU functional defect CPU_TC.106".
To enable this warning, the option --silicon-bug=cpu-tc106
must be
specified on command line.
For the description for this deviation see "Errata Sheet TC1767 AB, v1.0 dd 2008-03-19".
Whenever a load or store
instruction using a circular addressing mode is encountered, which is
not preceded by a nop, the assembler will give warning W829 "suspicious
instruction concerning CPU functional defect
CPU_TC.108".
To enable this warning, the option --silicon-bug=cpu-tc108
must be
specified on command line.
For the description for this deviation see "Errata Sheet TC1767ED AD, v1.0 dd 2008-07-04".
Whenever a load word
instruction is encountered, using circular addressing mode and
preceded by a store byte instruction, or when only a single
ip-instruction is in between such a load word instruction and a store
byte instruction, the assembler will give warning W830 "suspicious
instruction concerning CPU functional defect CPU_TC.109".
To enable this warning, the option --silicon-bug=cpu-tc109
must be
specified on command line.
Added support for functional deviations CPU TC.105, CPU TC.106, CPU TC.108 and CPU TC.109
The libraries have been rebuild, using the new compiler.
Copyright 2008 Altium BV