This appendix contains the following sections:
Introduction
Register Mapping
Code Translation
Porting from 8051 Assembly Code
XA Assembler as Translator
CPL Instruction
ARn Register
SP Usage
Indirect Addressing
Bit Addressing
8051 Compatible Instructions
Stack Management
8051 Compatible PSW51 Register
Typical 8051 Code
8051 to XA Translation Table
When you set a special translation option, the XA assembler translates 8051 instructions to the XA equivalents. In this translation mode the assembler can handle both XA and 8051 instructions. Instructions that are legal for both 80C1 and the XA are handled as 8051 instructions.
To enable the 8051 translation mode use the -r option: "Read 8051 instructions". By default the TASKING XA assembler reads XA instructions only. You can also use the controls READ8051 and NOREAD8051 to mark the beginning and end of an 8051 instruction block respectively.
The TASKING XA assembler is able to read XA and 8051 assembly input (.src or .asm) and generates TASKING XA object code (.obj) and a list file (.lst). This list file shows information about the opcode for the instructions, handling of generic instructions, cycle counting and so on. In 8051 translation mode information is included about the translated instructions. The following part of a list file clarifies this:
000000 14 MAIN_PR SEGMENT CODE 000000 15 RSEG MAIN_PR 000000 16 _main: 17 ADD A,R0 ; 8051 instruction 000000 0180 +17 ; ADD.B R4L,R0L 18 DEC R2 ; 8051 instruction 000002 A12F +18 ; ADDS.B R1L,#-1
The 8051 ADD- and DEC-instruction are replaced by the TASKING XA assembler with the XA equivalent ADD.B and ADDS.B. The list file can be helpful for rewriting your 8051 assembly source.
For assembler code it is in the first place important to map the 8051 registers to the XA register file. The four registers banks of the 8051 are duplicated to the XA register file. The eight 8-bit 8051 registers of each bank are mapped to the four 16-bits XA banked registers. The upper four XA registers are used for the common 8051 registers like the ACC, B, DPL and DPH. Register R7 of the XA is used as stack pointer register. Therefore, the SP register is mapped to R7L and R7H has to be set manually. Table H-1 shows the mapping of the 8051 registers to the XA register file.
XA registers | The 8051 registers mapped at the XA registers | |
R7 | SP | |
R6 | DPH | DPL |
R5 | ||
R4 | B | ACC |
R3 | R7 | R6 |
R2 | R5 | R4 |
R1 | R3 | R2 |
R0 | R1 | R0 |
H | L |
Table H-1: Register mappings
Register R0 to R3 of the XA are banked registers. This is compatible to the 8051, where register R0 to R7 are banked registers.
The code translation of 8051 instructions to XA instructions is very simple. With only one exception each instruction can be translated one to one on an XA instruction. The only exception is the XCHD instruction. To translate this 8051 instruction a sequence of XA instructions is being generated. The 8051 instruction XCHD is translated as follow:
;; 8051 XCHD ACC,@Ri ; Ri = [R0,R1]
;; XA PUSH.b R4H ; Use R4H as a temporary register MOV.b R4H,[Ri] ; Get second operand RR.b R4H,#4 ; Swap nibbles of this operand RR.b R4L,#4 ; Swap nibbles of the first operand (ACC) RL.w R4,#4 ; Rotate one nibble left, ; upper R4H nibble to R4L. MOV.b [Ri],R4H ; Store this result in data memory POP.b R4H ; Restore R4H
Section 9 in this Appendix contain a complete translation table for 8051 instructions. The TASKING XA assembler uses this translation table. The TASKING XA assembler is capable of reading 8051 instructions and translates these instructions to their XA equivalent. See for an explanation of how to use this TASKING XA assembler feature in section 5.
The route from 8051 assembly code to XA assembly code depends strongly on the design of your 8051 assembly code. Complicated stack manipulations, usage of bit patterns, absolute addressing and extensive usage of I/O facilities may encourage the need of reengineering your code. All of these possible problems are handled here.
As explained in section 3, the TASKING XA assembler has a 8051 translation feature. Information about instruction translation can be used to actually rewrite your code. The TASKING XA assembler is also helpful with the porting process by generating warnings for suspicious parts of code. These warnings are:
The following sections describe all these warnings.
The 8051 instruction 'CPL bit' is translated to its XA equivalent 'XOR.b direct,#data'. The assembler calculates the bit address based on the corresponding byte address and the 8-bits data value needed for the byte wise exchange (XCH.b). The XA assembler uses a notation: 'XOR.b bit' and generates a warning to emphasize the need to check the address and rewrite the notation.
In this way:
CPL C
is translated by the TASKING XA assembler as:
XCH.b C
this instruction is handled by the assembler as if it was:
XCH.b 400,#80H
The assembler generates a warning (W 179) that you actually have to check this address and add it to the new XA instruction yourself.
The TASKING XA assembler reckons the USING keyword. This way the assembler translates the ARn notation known by the TASKING 8051 assembler to a direct address in data memory in the range from 00H to 1FH. Notice that this will only work if the XA processor is set to 8051 compatibility mode. The TASKING XA assembler gives a warning to emphasize this (W 181).
The ARn notation makes register bank usage very quick. The USING keyword selects a register bank (0 - 3) and the assembler calculates a direct address for ARn. This feature is supported in the XA assembler when the 8051 translation mode is selected. The assembler generates a warning that this will only work if the XA processor runs in 8051 compatibility mode.
The XA assembler will detect any usage of the stack pointer register (SP) in 8051 instructions. The 8-bit stack pointer of the 8051 processor is translated to XA register R7L, while the assembler generates a warning that a suspicious translation has been done (W 178). Both the contents of R7L and R7H have to be checked.
Indirect addressing for the XA architecture can only be performed through the 16-bit registers. In 8051 compatibility mode indirect addressing by R0 and R1 has special support to be compatible with the 8051 indirect addressing. The first two bytes of the register file (R0L and R0H) are used to reflect the 8-bit 8051 registers R0 and R1. These registers are zero extended to 16-bits. The 8051 instructions:
MOV ACC,@R0 MOV B,@R1
Are replaced by:
MOV.b R4L,[R0] MOV.b R4H,[R1]
Where the XA architecture in compatibility mode reads:
MOV.b R4L,[ 00000000 bbbbbbbb ] ; bbbbbbbb equals R0L MOV.b R4H,[ 00000000 aaaaaaaa ] ; aaaaaaaa equals R0H
These 8-bit pointer operations may work, but it is better to replace these pointer operations to achieve save native XA code during the porting process. The TASKING XA assembler generates a warning on any 8051 indirect operation that is found (W 181).
The 8051 bit-addressable area of 128 bits is located at byte address 20H-2FH of the lower data RAM. Bit number 0 of the data byte at 20H has the bit-address 00H while bit 7 of address 2FH has the bit-address 7FH. In the XA architecture the bit-addressable space is expanded. Thirty-two bytes of each segment of data memory are bit addressable. The bit-addressable area is located at 20H-3FH while the bit addresses are from 100H for bit 0 of data address 20H to 1FFH for bit 7 of data address 3FH. Because of this the use of absolute bit-addresses in assembly code is dangerous. The assembler issues a warning to check the bit address (W 180). It is recommended to use symbolic names and let the TASKING locator assign the addresses to your bit variables.
For 8051 compatibility reasons five instruction were added to the XA architecture. These instructions are:
JN JNZ JMP[A+DPTR] MOVC A,[A+DPTR] MOVC A,[A+PC]
The TASKING XA assembler generates a warning when one of these instructions is used (W 182), because the resulting code may be non-functional and to encourage the usage of native XA code.
The stack allocation and management needs special attention when porting assembly code. First consider the differences between the 8051 stack and the XA stack:
The TASKING XA assembler translates the SP register to XA register R7L and a warning is generated to emphasize the need to check the stack pointer usage (W 178). On initialization of the stack pointer, the contents of register R7H has to be set and the stack pointer of the XA has to be initialized at the top of the stack. Besides the allocation of the stack and the initialization of the stack pointer, special attention is needed for stack adaptations, that means all instructions concerning the SP register, except POP and PUSH operations. So, thoroughly check the warnings of the assembler on SP usage in your 8051 code. Porting your 8051 stack to the XA stack is very easy if the only stack operations are the initialization of the stack and PUSH and POP operations. To be sure the stack is large enough, allocate as many words as your 8051 application allocated bytes.
The XA architecture includes a special function register that is compatible with the 8051 program status word register, PSW. This register is named PSW51 in the XA architecture. Because 8051 assembly code uses the name PSW for the 8051 program status word, the TASKING assembler include files include information of PSW as well as PSW51. In other words PSW has the same SFR space address as PSW51.
There are al lot of 8051 assembly code constructions that can lead to problems during the porting process; P2 external ram addressing, $-relative jumps, popping DPL and PDH for absolute jumps and so on. These kind of assembly code has to be checked and decoded to XA assembly code. The effort of work of the porting process needed is strongly dependent on this kind of typical 8051 code.
8051 Instruction | XA Translation |
Arithmetic operations | |
ADD A, Rn ADD A, #data8 ADD A,dir8 ADD A, @Ri ADDC A, Rn ADDC A, #data8 ADDC A,dir8 ADDC A, @Ri | ADD.b R, R ADD.b R, #data8 ADD.b R, direct ADD.b R, [R] ADDC.b R, R ADDC.b R, #data8 ADDC.b R, direct ADDC.b R, [R] |
SUBB A, Rn SUBB A, #data8 SUBB A, dir8 SUBB A, @Ri | SUBB.b R, R SUBB.b R, #data8 SUBB.b R, direct SUBB.b R, [R] |
INC Rn INC dir8 INC @Ri INC A INC DPTR | ADDS.b R, #1 ADDS.b direct, #1 ADDS.b [R], #1 ADDS.b R, #1 ADDS.w R, #1 |
DEC Rn DEC dir8 DEC @Ri DEC A | ADDS.b R, #-1 ADDS.b direct, #-1 ADDS.b [R], #-1 ADDS.b R, #-1 |
MUL AB DIV AB DA A | MULU.b R, R DIVU.b R, R DA R |
Logical operations | |
ANL A, Rn ANL A, #data8 ANL A, dir8 ANL A, @Ri ANL dir8, A ANL dir8, #data8 | AND.b R, R AND.b R, #data8 AND.b R, direct AND.b R, [R] AND.b direct, R AND.b direct, #data8 |
ORL A, Rn ORL A, #data8 ORL A, dir8 ORL A, @Ri ORL dir8, A ORL dir8, #data8 | OR.b R, R OR.b R, #data8 OR.b R, direct OR.b R, [R] OR.b direct, R OR.b direct, #data8 |
XRL A, Rn XRL A, #data8 XRL A, dir8 XRL A, @Ri XRL dir8, A XRL dir8, #data8 | XOR.b R, R XOR.b R, #data8 XOR.b R, direct XOR.b R, [R] XOR.b direct, R XOR.b direct, #data8 |
CLR A CPL A SWAP A | MOVS.b R, #0 CPL.b R RL.b R, #4 |
RL A RLC A RR A RRC A | RL.b R, #1 RLC.b R, #1 RR.b R, #1 RRC.b R, #1 |
CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C | CLR bit CLR bit SETB bit SETB bit XOR.b PSWL, #data8 XOR.b direct, #data8 ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C |
Data transfer | |
MOV A, Rn MOV A, #data8 MOV A, dir8 MOV A, @Ri MOV Rn, A MOV Rn, #data8 MOV Rn, dir8 MOV dir8, A MOV dir8, #data8 MOV dir8, Rn MOV dir8, dir8 MOV dir8, @Ri MOV @Ri, A MOV @Ri, dir8 MOV @Ri, #data8 MOV DPTR, #data16 | MOV.b R, R MOV.b R, #data8 MOV.b R, direct MOV.b R, [R] MOV.b R, R MOV.b R, #data8 MOV.b R, direct MOV.b direct, R MOV.b direct, #data8 MOV.b direct, R MOV.b direct, direct MOV.b direct, [R] MOV.b [R], R MOV.b [R], direct MOV.b [R], #data8 MOV.w R, #data16 |
XCH A, Rn XCH A, dir8 XCH A, @Ri XCHD A, @Ri | XCH.b R, R XCH.b R, direct XCH.b R, [R] a sequence (see section 3) |
PUSH dir8 POP dir8 | PUSH.b direct POP.b direct |
MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A | MOVX.b R, [R] MOVX.b R, [R] MOVX.b [R], R MOVX.b [R], R |
MOVC A, @A+DPTR MOVC A, @A+PC | MOVC.b A, [A+DPTR] MOVC.b A, [A+PC] |
Relative branches | |
SJMP rel8 | BR rel8 |
CJNE A, dir8, rel CJNE A, #data8, rel CJNE Rn, #data8, rel CJNE @Ri, #data8, rel | CJNE.b R, direct, rel CJNE.b R, #data8, rel CJNE.b R, #data8, rel CJNE.b [R], #data8, rel |
DJNZ Rn, rel DJNZ dir8, rel | DJNZ.b R, rel DJNZ.b direct, rel |
JZ rel JNZ rel JC rel JNC rel | JZ rel JNZ rel BCS rel BCC rel |
Jumps, Calls, Returns, and Misc. | |
NOP | NOP |
AJMP addr11 LJMP addr16 JMP @A+DPTR | JMP rel16 JMP rel16 JMP [A+DPTR] |
ACALL addr11 LCALL addr16 | CALL rel16 CALL rel16 |
RET RETI | RET RETI |
Table H-2: 8051 to XA instruction translations