G INSTRUCTION SET TABLE

1 Introduction

The XA uses a powerful and efficient instruction set, offering several different types of addressing modes. A versatile set of "branch" and "jump" instructions are available for controlling program flow based on register or memory contents. Special emphasis has been placed on the instruction support of structured high-level languages and real-time multi-tasking operating systems.

This appendix contains a table with the instructions provided in the XA microcontroller. The table lists the available instructions with their different addressing modes and briefly describes what each instruction does along with the number of bytes, and number of cycles required for each instruction. The formats have been chosen to optimize the length and execution speed of those instructions that would be used the most often in critical code. Only the first and sometimes the second byte of an instruction are used for operation encoding. The length of the instruction and the first execution cycle activity are determined from the first byte. Instruction bytes following the first two bytes (if any) are always immediate operands, such as addresses, relative displacements, offsets, bit addresses, and immediate data.

For a detailed description of the operation of each instruction, see the 16-bit 80C51XA Microcontrollers Data Handbook.

A separate table lists the summary of status flags updated by different instructions.

2 Instruction Set

Legend (Operands)

offset8 An 8-bit signed offset (immediate data in the instruction) that is added to a register to produce an absolute address.

offset16 A 16-bit signed offset (immediate data in the instruction) that is added to a register to produce an absolute address.

direct An 11-bit immediate address contained in the instruction.

#data4 4 bits of immediate data contained in the instruction. (range +7 to -8 for signed immediate data and 0-15 for shifts)

#data5 5 bits of immediate data contained in the instruction. (0-31 for shifts)

#data8 8 bits of immediate data contained in the instruction. (+127 to -128)

#data16 16 bits of immediate data contained in the instruction. (+32,767 to -32,768)

bit The 10-bit address of an addressable bit.

rel8 An 8-bit relative displacement for branches. (+254 to -256)

rel16 An 16-bit relative displacement for branches.(+65,534 to -65,536)

addr16 A 16-bit absolute branch address within a 64K code page.

addr24 A 24-bit absolute branch address, able to access the entire XA address space.

SP The current Stack Pointer (User or System) depending on the operation mode.

USP The User Stack Pointer.

SSP The System Stack Pointer

C Carry flag from the PSW.

AC Auxiliary Carry flag from the PSW.

V Overflow flag from the PSW.

N Negative flag from the PSW.

Z Zero flag from the PSW.

DS Data segment register. Holds the upper byte of the 24-bit data address space of the XA. Used mainly for local data segments.

ES Extra segment register. Holds the upper byte of the 24-bit data address space of the XA. Used mainly for addressing remote data structures.

direct Uses the current DS for data memory for the upper byte of the 24-bit address or none (uses only the low 16-bit address) for accessing the special functions register (SFR) space. The interpretation should be as below:
if (data range)
then (direct = (DS:direct)
if (sfr range)
then (direct) = (sfr)

Rs Source register.

Rd Destination register.

[ ] In the instruction mnemonic, indicates an indirect reference (e.g.: [R4] refers to the memory address pointed to by the contents of register 4).

[[ ]] Used to indicate Double-indirect addressing.

[R+] Used to indicate an automatic increment of the pointer register in some indirect addressing modes.

[WS:R] Indicates that the pointer register (R) is extended to a 24-bit pointer by the selected segment register (either DS or ES for all instructions except MOVC, which uses either PC 23-16 or CS).

Rlist A bitmap that represents each register in the register file during a PUSH or POP operation. These registers are R0-R7 for word or R0L-R7H for byte.

Legend (Cycle time)

PZ In Page 0

nt Not Taken

t Taken

Mnem. Operand Description Bytes Clocks
ADD Rd, Rs Add registers direct 2 3
ADD Rd, [Rs] Add register-indirect to register 2 4
ADD [Rd], Rs Add register to register-indirect 2 4
ADD Rd, [Rs+offset8] Add register-indirect with 8-bit offset to register 3 6
ADD [Rd+offset8], Rs Add register to register-indirect with 8-bit offset 3 6
ADD Rd, [Rs+offset16] Add register-indirect with 16-bit offset to register 4 6
ADD [Rd+offset16], Rs Add register to register-indirect with 16-bit offset 4 6
ADD Rd, [Rs+] Add register-indirect with auto increment to register 2 5
ADD [Rd+], Rs Add register-indirect with auto increment to register 2 5
ADD direct, Rs Add register to memory 3 4
ADD Rd, direct Add memory to register 3 4
ADD Rd, #data8 Add 8-bit immediate data to register 3 3
ADD Rd, #data16 Add 16-bit immediate data to register 4 3
ADD [Rd], #data8 Add 8-bit immediate data to register-indirect 3 4
ADD [Rd], #data16 Add 16-bit immediate data to register-indirect 4 4
ADD [Rd+], #data8 Add 8-bit immediate data to register-indirect with auto-increment 3 5
ADD [Rd+], #data16 Add 16-bit immediate data to register-indirect with auto-increment 4 5
ADD [Rd+offset8], #data8 Add 8-bit immediate data to register-indirect with 8-bit offset 4 6
ADD [Rd+offset8], #data16 Add 16-bit immediate data to register-indirect with 8-bit offset 5 6
ADD [Rd+offset16], #data8 Add 8-bit immediate data to register-indirect with 16-bit offset 5 6
ADD [Rd+offset16], #data16 Add 16-bit immediate data to register-indirect with 16-bit offset 6 6
ADD direct, #data8 Add 8-bit immediate data to memory 4 4
ADD direct, #data16 Add 16-bit immediate data to memory 5 4
ADDC Rd, Rs Add registers direct with carry 2 3
ADDC Rd, [Rs] Add register-indirect to register with carry 2 4
ADDC [Rd], Rs Add register to register-indirect with carry 2 4
ADDC Rd, [Rs+offset8] Add register-indirect with 8-bit offset to register with carry 3 6
ADDC [Rd+offset8], Rs Add register to register-indirect with 8-bit offset with carry 3 6
ADDC Rd, [Rs+offset16] Add register-indirect with 16-bit offset to register with carry 4 6
ADDC [Rd+offset16], Rs Add register to register-indirect with 16-bit offset with carry 4 6
ADDC Rd, [Rs+] Add register-indirect with auto increment to register with carry 2 5
ADDC [Rd+], Rs Add register-indirect with auto increment to register with carry 2 5
ADDC direct, Rs Add register to memory with carry 3 4
ADDC Rd, direct Add memory to register with carry 3 4
ADDC Rd, #data8 Add 8-bit immediate data to register with carry 3 3
ADDC Rd, #data16 Add 16-bit immediate data to register with carry 4 3
ADDC [Rd], #data8 Add 16-bit immediate data to register-indirect with carry 3 4
ADDC [Rd], #data16 Add 16-bit immediate data to register-indirect with carry 4 4
ADDC [Rd+], #data8 Add 8-bit immediate data to register-indirect and auto-increment with carry 3 5
ADDC [Rd+], #data16 Add 16-bit immediate data to register-indirect and auto-increment with carry 4 5
ADDC [Rd+offset8], #data8 Add 8-bit immediate data to register-indirect with 8-bit offset and carry 4 6
ADDC [Rd+offset8], #data16 Add 16-bit immediate data to register-indirect with 8-bit offset and carry 5 6
ADDC [Rd+offset16], #data8 Add 8-bit immediate data to register-indirect with 16-bit offset and carry 5 6
ADDC [Rd+offset16], #data16 Add 16-bit immediate data to register-indirect with 16-bit offset and carry 6 6
ADDC direct, #data8 Add 8-bit immediate data to memory with carry 4 4
ADDC direct, #data16 Add 16-bit immediate data to memory with carry 5 4
ADDS Rd, #data4 Add 4-bit signed immediate data to register 2 3
ADDS [Rd], #data4 Add 4-bit signed immediate data to register-indirect 2 4
ADDS [Rd+], #data4 Add 4-bit signed immediate data to register-indirect with auto-increment 2 5
ADDS [Rd+offset8], #data4 Add register-indirect with 8-bit offset to 4-bit signed immediate data 3 6
ADDS [Rd+offset16], #data4 Add register-indirect with 16-bit offset to 4- bit signed immediate data 4 6
ADDS direct, #data4 Add 4-bit signed immediate data to memory 3 4
AND Rd, Rs Logical AND registers direct 2 3
AND Rd, [Rs] Logical AND register-indirect to register 2 4
AND [Rd], Rs Logical AND register to register-indirect 2 4
AND Rd, [Rs+offset8] Logical AND register-indirect with 8-bit offset to register 3 6
AND [Rd+offset8], Rs Logical AND register to register-indirect with 8-bit offset 3 6
AND Rd, [Rs+offset16] Logical AND register-indirect with 16-bit offset to register 4 6
AND [Rd+offset16], Rs Logical AND register to register-indirect with 16-bit offset 4 6
AND Rd, [Rs+] Logical AND register-indirect with auto increment to register 2 5
AND [Rd+], Rs Logical AND register-indirect with auto increment to register 2 5
AND direct, Rs Logical AND register to memory 3 4
AND Rd, direct Logical AND memory to register 3 4
AND Rd, #data8 Logical AND 8-bit immediate data to register 3 3
AND Rd, #data16 Logical AND 16-bit immediate data to register 4 3
AND [Rd], #data8 Logical AND 8-bit immediate data to register-indirect 3 4
AND [Rd], #data16 Logical AND16-bit immediate data to register-indirect 4 4
AND [Rd+], #data8 Logical AND 8-bit immediate data to register-indirect and auto-increment 3 5
AND [Rd+], #data16 Logical AND16-bit immediate data to register-indirect and auto-increment 4 5
AND [Rd+offset8], #data8 Logical AND8-bit immediate data to register-indirect with 8-bit offset 4 6
AND [Rd+offset8], #data16 Logical AND16-bit immediate data to register-indirect with 8-bit offset 5 6
AND [Rd+offset16], #data8 Logical AND8-bit immediate data to register-indirect with 16-bit offset 5 6
AND [Rd+offset16], #data16 Logical AND16-bit immediate data to register-indirect with 16-bit offset 6 6
AND direct, #data8 Logical AND 8-bit immediate data to memory 4 4
AND direct, #data16 Logical AND16-bit immediate data to memory 5 4
ANL C, bit Logical AND bit to carry 3 4
ANL C, /bit Logical AND complement of a bit to carry 3 4
ASL Rd, Rs Logical left shift destination register by the value in the source register 2 See Note 1
ASL Rd, #data4 Logical left shift register by the 4-bit immediate value 2 See Note 1
ASR Rd, Rs Arithmetic shift right destination register by the count in the source 2 See Note 1
ASR Rd, #data4 Arithmetic shift right register by the 4-bit immediate count 2 See Note 1
BCC rel8 Branch if the carry flag is clear 2 6t/3nt
BCS rel8 Branch if the carry flag is set 2 6t/3nt
BEQ rel8 Branch if the zero flag is set 2 6t/3nt
BG rel8 Branch if greater than (unsigned) 2 6t/3nt
BGE rel8 Branch if greater than or equal to (signed) 2 6t/3nt
BGT rel8 Branch if greater than (signed) 2 6t/3nt
BKPT Cause the breakpoint trap to be executed. 1 23/ 19(PZ)
BL rel8 Branch if less than or equal to (unsigned) 2 6t/3nt
BLE rel8 Branch if less than or equal to (signed) 2 6t/3nt
BLT rel8 Branch if less than (signed) 2 6t/3nt
BMI rel8 Branch if the negative flag is set 2 6t/3nt
BNE rel8 Branch if the zero flag is not set 2 6t/3nt
BNV rel8 Branch if overflow flag is clear 2 6t/3nt
BOV rel8 Branch if overflow flag is set 2 6t/3nt
BPL rel8 Branch if the negative flag is clear 2 6t/3nt
BR rel8 Short unconditional branch 2 3
CALL [Rs] Subroutine call indirect with a register 2 8/ 5(PZ)
CALL rel16 Relative call (+/- 64K) 3 7/ 4(PZ)
CJNE Rd,direct,rel8 Compare direct byte to register and jump if not equal 4 10t/ 7nt
CJNE Rd,#data8,rel8 Compare immediate byte to register and jump if not equal 4 9t/6nt
CJNE Rd,#data16,rel8 Compare immediate word to register and jump if not equal 5 9t/6nt
CJNE [Rd],#data8,rel8 Compare immediate word to register-indirect and jump if not equal 4 10t/ 7nt
CJNE [Rd],#data16,rel8 Compare immediate word to register-indirect and jump if not equal 5 10t/7 nt
CLR bit Clear bit 3 4
CMP Rd, Rs Compare destination and source registers 2 3
CMP [Rd], Rs Compare register with register-indirect 2 4
CMP Rd, [Rs] Compare register-indirect with register 2 4
CMP [Rd+offset8], Rs Compare register with register-indirect with 8-bit offset 3 6
CMP [Rd+offset16], Rs Compare register with register-indirect with 16-bit offset 4 6
CMP Rd, [Rs+offset8] Compare register-indirect with 8-bit offset with register 3 6
CMP Rd,[Rs+offset16] Compare register-indirect with 16-bit offset with register 4 6
CMP Rd, [Rs+] Compare auto-increment register-indirect with register 2 5
CMP [Rd+], Rs Compare register with auto-increment register-indirect 2 5
CMP direct, Rs Compare register with memory 3 4
CMP Rd, direct Compare memory with register 3 4
CMP Rd, #data8 Compare 8-bit immediate data to register 3 3
CMP Rd, #data16 Compare 16-bit immediate data to register 4 3
CMP [Rd], #data8 Compare 8 -bit immediate data to register-indirect 3 4
CMP [Rd], #data16 Compare 16-bit immediate data to register-indirect 4 4
CMP [Rd+], #data8 Compare 8-bit immediate data to register-indirect with auto-increment 3 5
CMP [Rd+], #data16 Compare 16-bit immediate data to register-indirect with auto-increment 4 5
CMP [Rd+offset8], #data8 Compare 8-bit immediate data to register-indirect with 8-bit offset 4 6
CMP [Rd+offset8], #data16 Compare 16-bit immediate data to register-indirect with 8-bit offset 5 6
CMP [Rd+offset16], #data8 Compare 8-bit immediate data to register-indirect with 16-bit offset 5 6
CMP [Rd+offset16], #data16 Compare 16-bit immediate data to register-indirect with 16-bit offset 6 6
CMP direct, #data8 Compare 8-bit immediate data to memory 4 4
CMP direct, #data16 Compare 16-bit immediate data to memory 5 4
CPL Rd Complement (ones complement) register 2 3
DA Rd Decimal Adjust byte register 2 4
DIV.w Rd, Rs 16x8 signed register divide 2 14
DIV.w Rd, #data8 16x8 signed divide register with immediate word 3 14
DIV.d Rd, Rs 32x16 signed double register divide 2 24
DIV.d Rd, #data16 32x16 signed double register divide with immediate word 4 24
DIVU.b Rd, Rs 8x8 unsigned register divide 2 12
DIVU.b Rd, #data8 8X8 unsigned register divide with immediate byte 3 12
DIVU.w Rd, Rs 16X8 unsigned register divide 2 12
DIVU.w Rd, #data8 16X8 unsigned register divide with immediate byte 3 12
DIVU.d Rd, Rs 32X16 unsigned double register divide 2 22
DIVU.d Rd, #data16 32X16 unsigned double register divide with immediate word 4 22
DJNZ Rd,rel8 Decrement register and jump if not zero 3 8t/5nt
DJNZ direct,rel8 Decrement memory and jump if not zero 4 9t/6nt
FCALL addr24 Far call (anywhere in the 24-bit address space) 4 9/ 5(PZ)
FJMP addr24 Far jump (anywhere in the 24-bit address space) 4 6
JB bit,rel8 Jump if bit set 4 7t/4nt
JBC bit,rel8 Jump if bit set and then clear the bit 4 7t/4nt
JMP rel16 Long unconditional branch 3 6
JMP [Rs] Jump indirect to the address in the register (64K) 2 7
JMP [A+DPTR] Jump indirect relative to the DPTR 2 5
JMP [[Rs+]] Jump double-indirect to the address (pointer to a pointer) 2 8
JNB bit,rel8 Jump if bit not set 4 7t/4nt
JNZ rel8 Jump if accumulator not equal zero 2 7t/4nt
JZ rel8 Jump if accumulator equals zero 2 7t/4nt
LEA Rd, Rs+offset8 Load 16-bit effective address with 8-bit offset to register 3 3
LEA Rd, Rs+offset16 Load 16-bit effective address with 16-bit offset to register 4 3
LSR Rd, Rs Logical right shift destination register by the value in the source register 2 See Note 1
LSR Rd, #data4 Logical right shift register by the 4-bit immediate value 2 See Note 1
MOV Rd, Rs Move register to register 2 3
MOV Rd, [Rs] Move register-indirect to register 2 3
MOV [Rd], Rs Move register to register-indirect 2 3
MOV Rd, [Rs+offset8] Move register-indirect with 8-bit offset to register 3 5
MOV [Rd+offset8], Rs Move register to register-indirect with 8-bit offset 3 5
MOV Rd, [Rs+offset16] Move register-indirect with 16-bit offset to register 4 5
MOV [Rd+offset16], Rs Move register to register-indirect with 16-bit offset 4 5
MOV Rd, [Rs+] Move register-indirect with auto increment to register 2 4
MOV [Rd+], Rs Move register-indirect with auto increment to register 2 4
MOV direct, Rs Move register to memory 3 4
MOV Rd, direct Move memory to register 3 4
MOV [Rd+], [Rs+] Move register-indirect to register-indirect, both pointers auto-incremented 2 6
MOV direct, [Rs] Move register-indirect to memory 3 4
MOV [Rd], direct Move memory to register-indirect 3 4
MOV Rd, #data8 Move 8-bit immediate data to register 3 3
MOV Rd, #data16 Move 16-bit immediate data to register 4 3
MOV [Rd], #data8 Move 16-bit immediate data to register-indirect 3 3
MOV [Rd], #data16 Move 16-bit immediate data to register-indirect 4 3
MOV [Rd+], #data8 Move 8-bit immediate data to register-indirect with auto-increment 3 4
MOV [Rd+], #data16 Move 16-bit immediate data to register-indirect with auto-increment 4 4
MOV [Rd+offset8], #data8 Move 8-bit immediate data to register-indirect with 8-bit offset 4 5
MOV [Rd+offset8], #data16 Move 16-bit immediate data to register-indirect with 8-bit offset 5 5
MOV [Rd+offset16], #data8 Move 8-bit immediate data to register-indirect with 16-bit offset 5 5
MOV [Rd+offset16], #data16 Move 16-bit immediate data to register-indirect with 16-bit offset 6 5
MOV direct, #data8 Move 8-bit immediate data to memory 4 3
MOV direct, #data16 Move 16-bit immediate data to memory 5 3
MOV direct, direct Move memory to memory 4 4
MOV Rd, USP Move User Stack Pointer to register (system mode only) 2 3
MOV USP, Rs Move register to User Stack Pointer (system mode only) 2 3
MOV C, bit Move bit to the carry flag 3 4
MOV bit, C Move carry to bit 3 4
MOVC Rd, [Rs+] Move data from WS:Rs address of code memory to register with auto-increment 2 4
MOVC A, [A+DPTR] Move data from code memory to the accumulator indirect with DPTR 2 6
MOVC A, [A+PC] Move data from code memory to the accumulator indirect with PC 2 6
MOVS Rd, #data4 Move 4-bit sign-extended immediate data to register 2 3
MOVS [Rd], #data4 Add 4-bit sign-extended immediate data to register-indirect 2 4
MOVS [Rd+], #data4 Add 4-bit sign-extended immediate data to register-indirect with auto-increment 2 4
MOVS [Rd+offset8], #data4 Add register-indirect with 8-bit offset to 4-bit sign-extended immediate data 3 5
MOVS [Rd+offset16], #data4 Add register-indirect with 16-bit offset to 4- bit sign-extended immediate data 4 5
MOVS direct, #data4 Add 4-bit sign-extended immediate data to memory 3 3
MOVX Rd, [Rs] Move external data from memory to register 2 6
MOVX [Rd], Rs Move external data from register to memory 2 6
MUL.w Rd, Rs 16X16 signed multiply of register contents 2 12
MUL.w Rd, #data16 16X16 signed multiply 16-bit immediate data with register 4 12
MULU.b Rd, Rs 8X8 unsigned multiply of register contents 2 12
MULU.b Rd, #data8 8X8 unsigned multiply of 8-bit immediate data with register 3 12
MULU.w Rd, Rs 16X16 unsigned register multiply 2 12
MULU.w Rd, #data16 16X16 unsigned multiply 16-bit immediate data with register 4 12
NEG Rd Negate (twos complement) register 2 3
NOP No operation 1 3
NORM Rd, Rs Logical shift left destination register by the value in the source register until MSB set 2 See Note 1
OR Rd, Rs Logical OR registers 2 3
OR Rd, [Rs] Logical OR register-indirect to register 2 4
OR [Rd], Rs Logical OR register to register-indirect 2 4
OR Rd, [Rs+offset8] Logical OR register-indirect with 8-bit offset to register 3 6
OR [Rd+offset8], Rs Logical OR register to register-indirect with 8-bit offset 3 6
OR Rd, [Rs+offset16] Logical OR register-indirect with 16-bit offset to register 4 6
OR [Rd+offset16], Rs Logical OR register to register-indirect with 16-bit offset 4 6
OR Rd, [Rs+] Logical OR register-indirect with auto increment to register 2 5
OR [Rd+], Rs Logical OR register-indirect with auto increment to register 2 5
OR direct, Rs Logical OR register to memory 3 4
OR Rd, direct Logical OR memory to register 3 4
OR Rd, #data8 Logical OR 8-bit immediate data to register 3 3
OR Rd, #data16 Logical OR 16-bit immediate data to register 4 3
OR [Rd], #data8 Logical OR 8-bit immediate data to register- indirect 3 4
OR [Rd], #data16 Logical OR 16-bit immediate data to register- indirect 4 4
OR [Rd+], #data8 Logical OR 8-bit immediate data to register- indirect with auto-increment 3 5
OR [Rd+], #data16 Logical OR 16-bit immediate data to register- indirect with auto-increment 4 5
OR [Rd+offset8], #data8 Logical OR 8-bit immediate data to register- indirect with 8-bit offset 4 6
OR [Rd+offset8], #data16 Logical OR 16-bit immediate data to register- indirect with 8-bit offset 5 6
OR [Rd+offset16], #data8 Logical OR 8-bit immediate data to register- indirect with 16-bit offset 5 6
OR [Rd+offset16], #data16 Logical OR 16-bit immediate data to register-indirect with 16-bit offset 6 6
OR direct, #data8 Logical OR 8-bit immediate data to memory 4 4
OR direct, #data16 Logical OR16-bit immediate data to memory 5 4
ORL C, bit Logical OR a bit to carry 3 4
ORL C, /bit Logical OR complement of a bit to carry 3 4
POP direct Pop the memory content (byte/word) from the current stack 3 5
POP Rlist Pop multiple registers (byte/word) from the current stack 2 See Note 3
POPU direct Pop the memory content (byte/word) from the user stack 3 5
POPU Rlist Pop multiple registers (byte/word) from the user stack 2 See Note 3
PUSH direct Push the memory content (byte/word) onto the current stack 3 5
PUSH Rlist Push multiple registers (byte/word) onto the current stack 2 See Note 2
PUSHU direct Push the memory content (byte/word) onto the user stack 3 5
PUSHU Rlist Push multiple registers (byte/word)from the user stack 2 See Note 2
RESET Causes a hardware Reset, identical to an external Reset 2 8
RET Return from subroutine 2 8/ 6(PZ)
RETI Return from interrupt 2 10/ 8(PZ)
RL Rd, #data4 Rotate left register by the 4-bit immediate value 2 See Note 1
RLC Rd, #data4 Rotate left register though carry by the 4-bit immediate value 2 See Note 1
RR Rd, #data4 Rotate right register by the 4-bit immediate value 2 See Note 1
RRC Rd, #data4 Rotate right register though carry by the 4-bit immediate value 2 See Note 1
SETB bit Sets the bit specified 3 4
SEXT Rd Sign extend last operation to register 2 3
SUB Rd, Rs Subtract registers direct 2 3
SUB Rd, [Rs] Subtract register-indirect to register 2 4
SUB [Rd], Rs Subtract register to register-indirect 2 4
SUB Rd, [Rs+offset8] Subtract register-indirect with 8-bit offset to register 3 6
SUB [Rd+offset8], Rs Subtract register to register-indirect with 8- bit offset 3 6
SUB Rd, [Rs+offset16] Subtract register-indirect with 16-bit offset to register 4 6
SUB [Rd+offset16], Rs Subtract register to register-indirect with 16- bit offset 4 6
SUB Rd, [Rs+] Subtract register-indirect with auto increment to register 2 5
SUB [Rd+], Rs Subtract register-indirect with auto increment to register 2 5
SUB direct, Rs Subtract register to memory 3 4
SUB Rd, direct Subtract memory to register 3 4
SUB Rd, #data8 Subtract 8-bit immediate data to register 3 3
SUB Rd, #data16 Subtract 16-bit immediate data to register 4 3
SUB [Rd], #data8 Subtract 8-bit immediate data to register-indirect 3 4
SUB [Rd], #data16 Subtract 16-bit immediate data to register-indirect 4 4
SUB [Rd+], #data8 Subtract 8-bit immediate data to register-indirect with auto-increment 3 5
SUB [Rd+], #data16 Subtract 16-bit immediate data to register-indirect with auto-increment 4 5
SUB [Rd+offset8], #data8 Subtract 8-bit immediate data to register-indirect with 8-bit offset 4 6
SUB [Rd+offset8], #data16 Subtract 16-bit immediate data to register-indirect with 8-bit offset 5 6
SUB [Rd+offset16], #data8 Subtract 8-bit immediate data to register-indirect with 16-bit offset 5 6
SUB [Rd+offset16], #data16 Subtract 16-bit immediate data to register-indirect with 16-bit offset 6 6
SUB direct, #data8 Subtract 8-bit immediate data to memory 4 4
SUB direct, #data16 Subtract 16-bit immediate data to memory 5 4
SUBB Rd, Rs Subtract with borrow registers direct 2 3
SUBB Rd, [Rs] Subtract with borrow register-indirect to register 2 4
SUBB [Rd], Rs Subtract with borrow register to register-indirect 2 4
SUBB Rd, [Rs+offset8] Subtract with borrow register-indirect with 8- bit offset to register 3 6
SUBB [Rd+offset8], Rs Subtract with borrow register to register-indirect with 8-bit offset 3 6
SUBB Rd, [Rs+offset16] Subtract with borrow register-indirect with 16-bit offset to register 4 6
SUBB [Rd+offset16], Rs Subtract with borrow register to register-indirect with 16-bit offset 4 6
SUBB Rd, [Rs+] Subtract with borrow register-indirect with auto increment to register 2 5
SUBB [Rd+], Rs Subtract with borrow register-indirect with auto increment to register 2 5
SUBB direct, Rs Subtract with borrow register to memory 3 4
SUBB Rd, direct Subtract with borrow memory to register 3 4
SUBB Rd, #data8 Subtract with borrow 8-bit immediate data to register 3 3
SUBB Rd, #data16 Subtract with borrow 16-bit immediate data to register 4 3
SUBB [Rd], #data8 Subtract with borrow 8-bit immediate data to register-indirect 3 4
SUBB [Rd], #data16 Subtract with borrow 16-bit immediate data to register-indirect 4 4
SUBB [Rd+], #data8 Subtract with borrow 8-bit immediate data to register-indirect with auto-increment 3 5
SUBB [Rd+], #data16 Subtract with borrow 16-bit immediate data to register-indirect with auto-increment 4 5
SUBB [Rd+offset8], #data8 Subtract with borrow 8-bit immediate data to register-indirect with 8-bit offset 4 6
SUBB [Rd+offset8], #data16 Subtract with borrow 16-bit immediate data to register-indirect with 8-bit offset 5 6
SUBB [Rd+offset16], #data8 Subtract with borrow 8-bit immediate data to register-indirect with 16-bit offset 5 6
SUBB [Rd+offset16], #data16 Subtract with borrow 16-bit immediate data to register-indirect with 16-bit offset 6 6
SUBB direct, #data8 Subtract with borrow 8-bit immediate data to memory 4 4
SUBB direct, #data16 Subtract with borrow 16-bit immediate data to memory 5 4
TRAP #data4 Causes 1 of 16 hardware traps to be executed 2 23/ 19(PZ)
XCH Rd, Rs Exchange contents of two registers 2 5
XCH Rd, [Rs] Exchange contents of a register-indirect address with a register 2 6
XCH Rd, direct Exchange contents of memory with a register 3 6
XOR Rd, Rs Logical XOR registers 2 3
XOR Rd, [Rs] Logical XOR register-indirect to register 2 4
XOR [Rd], Rs Logical XOR register to register-indirect 2 4
XOR Rd, [Rs+offset8] Logical XOR register-indirect with 8-bit offset to register 3 6
XOR [Rd+offset8], Rs Logical XOR register to register-indirect with 8-bit offset 3 6
XOR Rd, [Rs+offset16] Logical XOR register-indirect with 16-bit offset to register 4 6
XOR [Rd+offset16], Rs Logical XOR register to register-indirect with 16-bit offset 4 6
XOR Rd, [Rs+] Logical XOR register-indirect with auto increment to register 2 5
XOR [Rd+], Rs Logical XOR register-indirect with auto increment to register 2 5
XOR direct, Rs Logical XOR register to memory 3 4
XOR Rd, direct Logical XOR memory to register 3 4
XOR Rd, #data8 Logical XOR 8-bit immediate data to register 3 3
XOR Rd, #data16 Logical XOR 16-bit immediate data to register 4 3
XOR [Rd], #data8 Logical XOR 8-bit immediate data to register- indirect 3 4
XOR [Rd], #data16 Logical XOR 16-bit immediate data to register-indirect 4 4
XOR [Rd+], #data8 Logical XOR 8-bit immediate data to register-indirect with auto-increment 3 5
XOR [Rd+], #data16 Logical XOR 16-bit immediate data to register-indirect with auto-increment 4 5
XOR [Rd+offset8], #data8 Logical XOR 8-bit immediate data to register-indirect with 8-bit offset 4 6
XOR [Rd+offset8], #data16 Logical XOR 16-bit immediate data to register-indirect with 8-bit offset 5 6
XOR [Rd+offset16], #data8 Logical XOR 8-bit immediate data to register-indirect with 16-bit offset 5 6
XOR [Rd+offset16], #data16 Logical XOR 16-bit immediate data to register-indirect with 16-bit offset 6 6
XOR direct, #data8 Logical XOR 8-bit immediate data to memory 4 4
XOR direct, #data16 Logical XOR16-bit immediate data to memory 5 4

Table G-1: Instruction set

1. For 8 and 16 bit shifts, it is 4+1 per additional two bits. For 32-bit shifts, it is 6+1 per additional two bits.

2. 3 clocks + 3 clocks/register.

3. 4 clocks +2 clocks/register.

Flags Setting

Instruction Flags Affected
C AC V N Z
ADD, ADDC, CMP, SUB, SUBB X X X X X
ADDS, MOVS - - - X X
AND, OR, XOR - - - X X
ASR, LSR * - - X X
branches, all bit operations, NOP - - - - -
Calls, Jumps, and Returns - - - - -
CJNE X - - X X
CPL - - - X X
DA * - - X X
DIV, MUL * - * X X
DJNZ - - - X X
LEA - - - - -
MOV, MOVC, MOVX - - - X X
NEG - - X X X
NORM - - - X X
PUSH, POP - - - - -
RESET * * * * *
RL, RR - - - X X
RLC, RRC * - - X X
SEXT - - - - -
TRAP, BKPT - - - - -
XCH - - - - -
ASL * - X X X

Table G-2: Flags setting

-: flag not updated.
X: flag updated according to the standard definition.
*: flag update is non-standard, refer to the individual instruction description.
Explicit writes to PSW flags takes precedence over flag updates.


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