8 INSTRUCTION SET

This chapter contains the following sections:

Introduction
Instruction Set
Arithmetic Instructions
Logical Instructions
Data Transfer Instructions
Boolean Bit Manipulation Instructions
Program Branching Instructions
Exception / Trap Instructions
Generic Instructions
Generic Branch Instructions
The Hardware Instruction Set

8.1 Introduction

The asxa XA assembler accepts all the assembly language instruction mnemonics defined for the XA while maintaining some existing 8051 microcontroller instructions. The mnemonics are listed in the tables below.

For a complete list of all instructions with mnemonics, operands, opcode format and states refer to the 16-bit 80C51XA Microcontrollers (eXtended Architecture) Data Handbook or the table in appendix Instruction Set Table.

The assembler also recognizes generic instructions. A separate section describes these instructions.

8.2 The Instruction Set

This section contains a summary of the XA instruction set. The instruction set can be subdivided in instruction classes as follows.

8.2.1 Arithmetic Instructions

Mnemonic Operation
add Add
addc Add with Carry
adds Add Signed
asl Arithmetic Shift to Left
asr Arithmetic Shift to Right
cmp Compare
da Decimal Adjust byte register
div.w Divide word
div.d Divide double word
divu.b Divide byte Unsigned
divu.w Divide word Unsigned
divu.d Divide double word Unsigned
lea Load Effective Address
mul.w Multiply word
mulu.b Multiply byte Unsigned
mulu.w Multiply word Unsigned
neg Negate register
sext Sign Extend to register
sub Subtract
subb Subtract with borrow

Table 8-1: Arithmetic instructions

8.2.2 Logical Instructions

Mnemonic Operation
and Logical AND
cpl Complement register
lsr Logical Shift Right
norm Logical Shift Left until MSB set
or Logical OR
rl Rotate left
rlc Rotate left through carry
rr Rotate right
rrc Rotate through carry
xor Logical Exclusive-OR

Table 8-2: Logical instructions

8.2.3 Data Transfer Instructions

Mnemonic Operation
mov Move
movc Move code
movs Move sign extended
movx Move external data
push Push onto current stack
pushu Push onto user stack
pop Pop from current stack
popu Pop from user stack
xch Exchange contents

Table 8-3: Data transfer instructions

8.2.4 Boolean Bit Manipulation Instructions

Mnemonic Operation
anl
anl/
Logical AND bit to Carry
Logical AND complement of bit to Carry
clr Clear bit
mov Move bit to Carry
Move Carry to bit
orl
orl/
Logical OR bit to Carry
Logical OR complement of bit to Carry
setb Set bit

Table 8-4: Boolean bit manipulation instructions

8.2.5 Program Branching Instructions

Mnemonic Operation
bcc Branch if Carry is clear
bcs Branch if Carry is set
beq Branch if Equal Zero
bne Branch if Not Equal Zero
bg Branch if Greater than (unsigned)
bge Branch if Greater than or Equal (signed)
bgt Branch if Greater Than (signed)
bl Branch if Less than or equal (unsigned)
ble Branch if Less than or Equal (signed)
blt Branch if Less Than (signed)
bmi Branch if Minus
bpl Branch if Plus
bnv Branch if No Overflow
bov Branch if Overflow
br Branch Unconditionally
call Subroutine or relative call
call.l Subroutine or relative call
cjne Compare and jump if not equal
djnz Decrement and jump if not zero
fcall Far call
fjmp Far jump
jb Jump if bit set
jbc Jump if bit set and clear bit
jmp Jump
jmp.l Jump
jnb Jump if bit Not set
jnz Jump if acculmulator not equal zero
jz Jump if acculmulator equals zero
nop No operation
ret Return from subroutine
reti Return from interrupt

Table 8-5: Program branching instructions

8.2.6 Exception / Trap Instructions

Mnemonic Operation
bkpt Breakpoint Trap
reset Hardware Reset
trap Hardware Trap

Table 8-6: Exception / trap instructions

8.3 Generic Instructions

The XA assembler supports various forms of generic instructions. For these generic instructions the assembler automatically selects the shortest sequence of available hardware instructions based on the operand addressing modes and the operand values.

8.3.1 Generic Branch Instructions

The assembler recognizes generic branch instructions. All XA branch instructions with a relative addressing mode are made generic. Generic instructions can be disabled with the assembler option _OJ or with the assemlber control $OPTIMIZE.

Based on the operand size and/or relative branch range the assembler decides whether to use the short, long or far instruction format. The assembler uses three different strategies to support generic branches.

The far instruction format is only used in Large-Memory mode. The assembler control [NO]ZPAGE indicates if code is meant for XA Page-Zero or Large-Memory mode.

The three different groups of generic branches are defined as:

1. If the XA architecture supports an inverse instruction for a conditional branch instruction. Then, the far and long form of the generic branch instruction invert the branch condition, and branch over an unconditional jump, which jumps to the target address. The unconditional jump is either a long jump or a far jump.

Example:

2. If no reverse instruction is available for a conditional branch instruction. Then, if the generic branch condition is true, the far and long form of the generic branch instruction, branches to an unconditional jump, which jumps to the target address. Otherwise if the branch condition is false, an unconditional branch is done over the unconditional jump. The unconditional jump is either a long or far jump.

Example:

3. In case of unconditional generic branches. The generic instruction can be replaced by one of the short, long, of far jump instructions supported by the XA architecture.

Example:

Generic branch instruction groups are listed in the following table:

Group Mnemonic Description
1 BCS Branch if the carry flag is set
BEQ Branch if the zero flag is set
BNE Branch if the zero flag is not set
BG Branch if greater than (unsigned)
BGE Branch if greater then or equal to (signed )
BGT Branch if greater then (signed)
BL Branch if less then or equal to (unsigned)
BLE Branch if less then or equal to (unsigned)
BLT Branch if less than (signed)
BMI Branch if the negative flag is set
BPL Branch if the negative flag is clear
BNV Branch if overflow flag is clear
BOV Branch if the overflow flag is set
JB Jump if bit set
1 JNB Jump if bit not set
JNZ Jump if accumulator not equal zero
JZ Jump if accumulator equals zero
2 JBC Jump if bit set and then clear the bit
CJNE Compare and jump if not equal
DJNZ Decrement and jump if not zero
3 BR Short unconditional branch
JMP Long unconditional branch
CALL Relative call

Table 8-7: Generic branch instructions

8.4 The Hardware Instruction Set

Many instructions described in the XA data book are generic instructions. The instructions operate on byte, word and sometimes double word operands. To indicate that an instruction operates on a byte, word or double word, a number of hardware mnemonics have been defined in the XA data handbook.

Logically associated hardware mnemonics are combined in one generic mnemonic. For example, the hardware mnemonics ADD.B and ADD.W are replaced by the software mnemonic ADD. Depending on the combination of operands, the assembler determines which opcode is entered in the instruction format, e.g. MOV R0,R1 is always words-size.

Not every combination of operands uniquely identifies whether the instruction is intended for byte or word size operations. For indirect-immediate, direct-immediate, direct-direct, etcetera, operand pairs, the assembler cannot deduce which instruction format should be used. In these cases the mnemonic must identify the operand size.

Generic Mnemonic Hardware Mnemonic Operation Type
ADD ADD.B (Add)
ADD.W
Byte
Word
ADDC ADDC.B (Add with Carry)
ADDC.W
Byte
Word
ADDS ADDS.B (Add Signed)
ADDS.W
Byte
Word
AND AND.B (Logical And)
AND.W
Byte
Word
ASL ASL.B (Arithmetic Shift Left)
ASL.W
ASL.D
Byte
Word
Double word
ASR ASR.B (Arithmetic Shift Right)
ASR.W
ASR.D
Byte
Word
Double word
CJNE CJNE.B (Compare jump if not equal)
CJNE.W
Byte
Word
CMP CMP.B (Compare)
CMP.W
Byte
Word
CPL CPL.B (Complement)
CPL.W
Byte
Word
DJNZ DJNZ.B (Decrement jump if not zero)
DJNZ.W
Byte
Word
LSR LSR.B (Logical Shift Right)
LSR.W
Byte
Word
MOV MOV.B (Move)
MOV.W
Byte
Word
MOVC MOVC.B (Move Code)
MOVC.W
Byte
Word
MOVS MOVS.B (Move Signed)
MOVS.W
Byte
Word
NEG NEG.B (Negate)
NEG.W
Byte
Word
NORM NORM.B (Shift left until MSB set)
NORM.W
NORM.D
Byte
Word
Double word
OR OR.B (Logical Or)
OR.W
Byte
Word
POP POP.B (Pop Byte from current stack)
POP.W (Pop Word from current stack)
Byte
Word
POPU POPU.B (Pop Byte from user stack)
POPU.W (Pop Word from user stack)
Byte
Word
PUSH PUSH.B (Push Byte on current stack)
PUSH.W (Push Word on current stack)
Byte
Word
PUSHU PUSHU.B (Push Byte on user stack)
PUSHU.W (Push Word on user stack)
Byte
Word
RL RL.B (Rotate Left)
RL.W
Byte
Word
RLC RLC.B (Rotate Left through Carry)
RLC.W
Byte
Word
RR RR.B (Rotate Right)
RR.W
Byte
Word
RRC RRC.B (Rotate Right through Carry)
RRC.W
Byte
Word
SEXT SEXT.B (Sign Extend)
SEXT.W
Byte
Word
SUB SUB.B (Subtract)
SUB.W
Byte
Word
SUBB SUBB.B (Subtract with Borrow)
SUBB.W
Byte
Word
XCH XCH.B (Exchange contents)
XCH.W
Byte
Word
XOR XOR.B (Exclusive Or)
XOR.W
Byte
Word

Table 8-8: Hardware instruction set


Copyright © 2000 TASKING, Inc.