Infineon/TASKING TriCore™ AURIX™ Webinar Series - Session IV – Cache Performance Analysis via Trace

An effi­cient uti­liza­tion of on-chip Cache Mem­o­ries can sig­nif­i­cant­ly enhance the per­for­mance of an embed­ded sys­tems. The Infi­neon Tri­Core™ AURIX™ micro­con­troller fea­tures both tight­ly-cou­pled pro­gram as well as data caches.

In this Webi­nar we first explain briefly how caches work in gen­er­al. We then pro­vide some basic guid­ance for how and when to use caches in AURIX™ devices.  In the sec­ond part of the Webi­nar we demon­strate how the Data Cache Per­for­mance can be ana­lyzed by means of trace, by mea­sur­ing para­me­ters such as func­tion run­time, but also para­me­ters such as Cache Hit/Miss ratios and Clocks per Instruc­tion (CPI) over time. 

Who:

Matthias Mar­quardt, Micro­con­troller FAE, Infi­neon Ger­many 

Armin Stingl, Head of Appli­ca­tion Engi­neer­ing, TASKING Ger­many