SoC Boot Up Timing Analysis using Arm System Trace Macrocell

This webi­nar focus­es on the pro­fil­ing of a boot-up process on Cor­tex-A bases Sys­tem-On-Chips (SoCs), start­ing from 1st stage boot­load­ers until the start­up of a Linux ker­nel; how the ARM Sys­tem Trace Macro­cell (STM) can be uti­lized for trac­ing a boot process dis­trib­uted across mul­ti­ple cores, e.g. Cor­tex-R7 boot core and Cor­tex-A53 appli­ca­tion cores.

Who: Oton Pavlic, Sys­tems Engi­neer, TASKING Labs, Slove­nia

Time­line: 

• 2:59 Agen­da and moti­va­tion
• 5:04 Intro­duc­tion to ARM Sys­tem Trace Macro­cell (STM)
• 7:06 Intro­duc­tion to SoC Boot-up Process (R-Car M3)
• 9:24 Boot­loader Instru­men­ta­tion demo
• 20:19 winIDEA Ana­lyz­er Con­fig­u­ra­tion
• 22:07 Two ways of winIDEA Trace Ana­lyz­er STM Con­fig­u­ra­tion (XML file and GUI method)
• 23:00 winIDEA Trace Ana­lyz­er STM Con­fig­u­ra­tion - GUI method
• 25:11 Trace Record­ing and results 25:52 Con­clu­sion
• 27:47 Answers and Ques­tions

Who should watch?

Auto­mo­tive soft­ware devel­op­ers, sys­tem archi­tects, soft­ware inte­gra­tors and test engi­neers who want to under­stand and opti­mize the tim­ing of the SoC boot-up process. This webi­nar aims at users who are devel­op­ing boot­load­ers for Cor­tex-A based SoCs.

Why should you watch?

In pre­vi­ous webi­na­rs we have dis­cussed the impor­tance of tim­ing-analy­sis via hard­ware trac­ing in mod­ern appli­ca­tions. The goal of this webi­nar is to give users a full under­stand­ing of the nec­es­sary steps start­ing from the instru­men­ta­tion of the boot­load­ers, con­fig­ur­ing the trace tool until the actu­al record­ing on the tar­get SoC. The con­cept will be demon­strat­ed on a Rene­sas R-Car H3 SoC.