TASKING TriCore Toolchain v1.5r3 (patch version)

README

SUMMARY

This readme describes a patch for TASKING TriCore toolchain versions v1.5r1 and v1.5r2. This pack contains workarounds for new Silicon Bugs, while the workarounds for some of the existing Silicon Bugs have been changed.

The following parts are described:

The reasons for releasing this patch are:


INSTALLATION GUIDELINES

Most likely you have the TASKING TriCore toolchain v1.5r1 or v1.5r2 installed already. If this is not the case yet, then do so first. Next extract the zip file while using the product directory as destination. Please be aware that the original components will be overwritten in this process.


EDE

In the EDE menu: Project | Project Options... | Processor | Bypasses, the new Silicon Bugs are listed. Note that at this moment there are both entries for COR13, COR14, COR17 as well as for CPU_TC.030, CPU_TC.031 and CPU_TC.034 available. For instance the workaround for COR14 still is to 'disable all interrupts during execution of a divide', while the workaround for CPU_TC.031 is changed in 'inserting an ISYNC instruction before a LOOP instruction. In the end the old Silicon Bug naming convention (CORxx) will become obsolete.

Notes for v1.5r1 users:

You can navigate through the different options dialogs via an expandable tree view as you are familiar with from other Windows based applications. This new way of presenting the options guarantees that you won't loose the complete overview and was introduced in v1.5r2 of the TASKING TriCore toolchain.

In the EDE menu: Project | Project Options... | Processor | Processor Definition | CPU type, you can select TC1910 and TC1912. This selection should however be avoided since the TC1910 and TC1912 were not supported in version v1.5r1 of the TASKING TriCore toolchain.


C COMPILER

cpu_tc.013

The compiler will generate an ISYNC instruction in case a 16-bit load/store address register instruction (instructions: LD16.A en ST16.A) is followed by a lower context load/store instruction (instructions: LDLCX and STLCX).

cpu_tc.030 (previously known as cor13)

The compiler will generate an ISYNC instruction in between the DVSTEP or DVSTEP.U instruction and the LOOP instruction. The former workaround was to generate a NOP instruction.

cpu_tc.031 (previously known as cor14)

The compiler will generate an ISYNC instruction prior to the loop instruction. The former workaround was to disable all interrupts during execution of any divide instruction.

cpu_tc.034 (previously known as cor17)

The compiler will generate an ISYNC instruction after each DSYNC. The former workaround was to generate a NOP instruction.

cpu_tc.048

The compiler inserts a NOP before each indirect jump or call instruction (JI, JLI, CALLI).
The compiler inserts a NOP instruction before a RET or RET16 if there is just one single integer instruction in the subroutine or if the subroutine does not contain any instructions (apart from the RET) at all.

cpu_tc.050

The compiler will insert a NOP instruction between a multicycle integer instruction and a load instruction.

tc113_cpu11

The compiler inserts a NOP before each indirect jump instruction (JI).

tc113_cpu16

The compiler inserts a NOP before each indirect jump or call instruction (JI, JLI, CALLI).
The compiler inserts a NOP instruction before a RET or RET16 if there is just one single integer instruction in the subroutine or if the subroutine does not contain any instructions (apart from the RET) at all.


ASSEMBLER

cpu_tc.013

The assembler will give a warning in case a 16-bit load/store address register instruction (instructions: LD16.A en ST16.A) is followed by a lower context load/store instruction (instructions: LDLCX and STLCX).

cpu_tc.030 (previously known as cor13)

The assembler gives a warning if a DVSTEP or DVSTEP.U instruction directly is followed by a loop instruction.

cpu_tc.031 (previously known as cor14)

The assembler gives a warning if the LOOP instruction is not preceded by an ISYNC instruction.

cpu_tc.034 (previously known as cor17)

The assembler gives a warning if a DSYNC instruction is not followed by an ISYNC.

cpu_tc.048

The assembler generates a warning if a JI, JLI or CALLI instruction is not preceded by a NOP instruction.
The assembler gives a warning when there is just one instruction, or none instruction at all, between a label and a return instruction.

cpu_tc.050

The assembler gives a warning if a multicycle integer instruction is directly followed by a load instruction.

tc113_cpu11

The assembler generates a warning if a JI instruction is not preceded by a NOP instruction.

tc113_cpu16

The assembler generates a warning if a JI, JLI or CALLI instruction is not preceded by a NOP instruction.
The assembler gives a warning when there is just one instruction, or none instruction at all, between a label and a return instruction.


LIBRARIES

The include files 'function_entry.asm_functional_problem_workaround' and 'loop_before.asm_functional_problem_workaround' have been updated and other code in the libraries have been changed as well to prevent new silicon bugs to trigger. The libraries are rebuild, using the new compiler and assembler.


LINKER/LOCATOR SCRIPT FILES

cpu_tc.043

The locator will not use the last 16 bytes of any segment. This is taken care of in the tri.cpu file, by reserving these areas.

cpu_tc.051

The locator will use more than one section for context stores if the required CSA area exceeds the 4k. Each section will have a maximum size of 4k and will start on a 8k boundaries. This is taken care of in the linker/locator script files tri.dsc and tri.cpu.


UTILITIES

Control Program

You can pass all new silicon bugs to the control program by using the -z option. The control program recognizes the silicon bugs and passes the option on, to the correct tool(s).

Copyright 2003 Altium BV