This release note describes the changes and new features of all TASKING TriCore products
since v2.3r1.
The following parts are described:
The solved and known problems are not part of this release note, they are described in solved_2_4r1.html (delivered with the software package).
The main reasons for this release are:
To bypass this CPU functional problem, the compiler directs certain program flow instructions, such as RET, RFE, CALL and JI, running in SPRAM (scratch pad ram) via a stub located in safe memory. In order to be able to tell the compiler that certain code is predetermined for SPRAM, the pragma spram and option --spram are introduced.
If the compiler encounters "#pragma spram" or if the option --spram is used and the workaround for silicon bug CPU TC.103 is activated, the compiler will start generating stubs for certain program flow instructions. These stubs will be placed in sections with unique names and are then collected in the LSL file and located in safe non-SPRAM memory.
If the compiler encounters "#pragma spram" or if option --spram is used and the workaround for silicon bug CPU TC.103 is not activated, the pragma or option is ignored. It is the responsibility of the user to use the pragma or option appropriately.
Note: Infineon has rectified this functional deviation in the latest stepping of the affected derivatives. For this reason the workaround for this deviation is not activated. To activate this workaround, specify the option --silicon-bug=cpu-tc103 when invoking the tools.
To bypass this CPU functional problem, the compiler inserts a NOP instruction before a double-word load instruction using circular addressing mode (LD.D instruction).
There is no assembler check for this functional deviation, since the assembler has no knowledge whether code is located in SPRAM or not. Therefore no reasonable check is possible.
The assembler gives a warning when a a double-word load instruction using circular addressing mode (LD.D instruction) is not preceded by a NOP instruction.
The part of the assembler that takes care of functional problem pattern recognition has been redesigned. This makes the assembler better prepared for recognizing more complex patterns. See also the description of pr34638.
To bypass this CPU functional problem, a preprocessor define is used in the tc*.lsl linker script files. The linker will collect the stubs as generated by the C compiler and locate them in safe non-SPRAM memory. Furthermore it is tested if (the start of) the interrupt and trap table are located at safe addresses.
Safe non-SPRAM addresses are defined as any address except:
bit [15:14] = 11b, for derivatives TC1130, TC1115, TC1110
bit [14:13] = 11b, for derivatives TC1762, TC1764, TC1766
The latest version of Infineon's Device Access Server (DAS), version v2.4, has been included in the product. This software is automatically installed when installing the TASKING TriCore toolchain. During the installation of DAS, the processes das_server_jtag.exe and das_dashpas.exe are started. When you have a firewall active, you may get alerts for this.
The DAS software now replaces the former and obsolete OCDS/JTAG system. It allows you to connect to a target board by means of the parallel port (Windows NT/2000/XP) or by means of an USB wiggler (Windows 2000/XP). DAS is available for Windows only.
The latest version of Infineon's TSIM simulator, version v1.4.5, has been included in the product. This new version is better configurable regarding memories and derivatives and allows the user to model the memory map of any TriCore derivative. Check out the TSIM user guide "issugv2.0.pdf" for further details.
When using the integrated environment EDE this configuration is automatically generated in a local MConfig file. The memory set up can be changed in the EDE menu: "Project | Project Options... | CrossView Pro | Simulator".
Copyright 2006 Altium BV