RISC‑V Software Development tools

A soft­ware develop­ment envi­ron­ment con­tain­ing a com­pil­er toolset for RISC‑V based devices.

The TASKING RISC‑V toolset is designed for reli­able embed­ded soft­ware develop­ment on RISC‑V based devices sup­port­ing a vari­ety of appli­ca­tions from auto­mo­tive to super­com­put­ers, with future FuSa and cyber­se­cu­ri­ty cer­ti­fi­ca­tions tai­lored to mar­ket demand.

TASK­ING’s RISC‑V tool suite includes com­pi­la­tion, sta­t­ic analy­sis, debug­ging, trac­ing, tim­ing, cov­er­age analy­sis tools, and tar­get libraries, offer­ing a com­pre­hen­sive solu­tion for sys­tems develop­ment.

The com­pil­er sup­ports a wide range of ISA exten­sions, allow­ing design­ers to eval­u­ate the impact of ISA changes on opti­miza­tion objec­tives like code size, speed, power con­sump­tion, per­for­mance, and sil­i­con area, pro­vid­ing a holis­tic view for sys­tem effi­cien­cy opti­miza­tion.

Vir­tu­al SoC develop­ment is sup­port­ed via inter­op­er­abil­i­ty with Syn­op­sys VDK and nSIM, and other vir­tu­al pro­to­type ven­dors, while phys­i­cal SoCs are sup­port­ed via TASKING Blue­Box debug­ger hard­ware.

TASKING is col­lab­o­rat­ing with IP and sil­i­con sup­pli­ers to ensure auto­mo­tive grade tools are avail­able before sil­i­con is avail­able. 

Prod­uct Brief
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Performance

Gen­er­ate effi­cient code sup­port­ing all rat­i­fied ISA exten­sions.
Code gen­er­a­tion based on com­bi­na­tion of Base ISA, ISA-exten­sions and core micro-archi­tec­ture.


Reliability

Prod­uct develop­ment in con­for­mance with ASPICE Level 2 com­pli­ant process­es.
Con­sis­tent­ly pass­es ver­i­fi­ca­tion tests includ­ing com­mer­cial, open-source and inter­nal­ly gen­er­at­ed test suites.
Imple­ments safe and secure com­pil­er opti­miza­tion strate­gies.


Safety &
Cybersecurity

FuSa and Cyber­se­cu­ri­ty com­pli­ance cer­tifi­cates will become avail­able on mar­ket demand.
Qual­i­fied to sat­is­fy ISO 26262, IEC 61508, ISO 25119, EN 50657, ISO 13849, and Cyber­se­cu­ri­ty stan­dard ISO/SAE 21434.
Pre­vents the appli­ca­tion of ‘un-safe’ opti­miza­tions based on unde­fined behav­iors in the user’s source code.

IDE and C/C++ Optimizing Compilers

Opti­mal device sup­port. The com­pil­er auto­mat­i­cal­ly adapts its code gen­er­a­tion and opti­miza­tion strate­gies based on the select­ed com­bi­na­tion of Base ISA, ISA-exten­sions and core micro-archi­tec­ture.
Gen­er­ates com­pact code, sup­port­ing all rat­i­fied ISA exten­sions to reduce code size.
Bal­anced opti­miza­tion trade­offs, so the com­pil­er deliv­ers fast-exe­cut­ing code while main­tain­ing a com­pact mem­o­ry foot­print.

Safety and Security

Safe­ty and Secu­ri­ty Man­u­al pro­vides easy to use guid­ance for safe and secure tool use. No addi­tion­al tool qual­i­fi­ca­tion efforts required by the user.
Built-in sta­t­ic analy­sis to ensure your source code com­plies with MISRA and CERT safe and secure cod­ing guide­lines.
Based on TASKING’s pro­pri­etary Viper com­pil­er develop­ment frame­work, the same tech­nol­o­gy that under­lies all TASKING’s com­pil­er toolsets.

Debugger

Sup­ports inno­v­a­tive debug and soft­ware analy­sis tools used for vir­tu­al and phys­i­cal SoC develop­ment.
Tar­get con­nec­tion with fam­i­ly of TASKING Blue­Boxs: iC7mini, iC7pro, iC7max.
Pro­vides all fea­tures required to col­lect evi­dence for safe­ty cer­ti­fi­ca­tion.

Supported RISC‑V Development

Vir­tu­al pro­to­type sup­port with Syn­op­sys® VDK, Syn­op­sys nSIM, and MachineWare SIM‑V™
Phys­i­cal MCU sup­port for Andes, GigaDe­vice, MicroChip and SiFive 
Andes RISC‑V IP sup­port: Andes N25F-SE and D25F-SE (except sup­port for Andes DSP exten­sion) IPs
Syn­op­sys RISC‑V IP sup­port: RMX and RHX series

Con­tact us if you inter­est­ed in eval­u­at­ing Beta ver­sions of the VX-toolset for RISC‑V.

Con­tact us if you inter­est­ed in eval­u­at­ing Beta ver­sions of the VX-toolset for RISC‑V.

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