This release note describes the changes and new features of all TASKING TriCore products
since v2.2r1.
The following parts are described:
The solved and known problems are not part of this release note, they are described in
solved_2_3r1.html.
The main reasons for this release are:
New TriCore derivatives are support within EDE, within menu 'Project | Project Options...' page 'Processor | Processor Definition':
In order to build the examples for the new derivatives without external memory, there is an easy workaround to prevent error messages within the linking phase. For all derivatives without external memory (TC116X, TC1762, TC1764 and TC1766) you need to make the following adjustment:
Go to menu "Project | Project Options..." and go to the page "Linker | Script File | Internal Memory". On this page change the SPRAM in such a way that the column "Alloc" gets the value ON and the column "Type" gets the value ROM.
Open your own project LSL file or open the included "<derivative_name>.lsl" file (present in the include.lsl subdirectory of the product). Adjust the type of the SPRAM into ROM:
memory spram
{
...
type = rom;
...
}
Within menu 'Project | Project Options...' page 'Processor | Bypasses' the new silicon bug workarounds can be found.
No new/changed features.
By default the compiler generates a 4 byte alignment for sections, this is done because the default initialization code does not know where code ends up and hardware could require a word aligned read/access to the memory. With the option --no-default-section-alignment, sections are no longer forced to a 4 byte alignment.
Please note, this means that you will have to use your own initialization code!
Furthermore you will have to remove the copy_unit = 4 part of the copytable declaration
within the LSL file.
| Pragma | Description |
| section_per_data_object | All data objects get their own section, using naming scheme like "prefix.module_name.<symbol name>" |
| section_name_with_symbol | All section renaming pragma's will use a renaming scheme like "prefix.symbol_name.<pragma value>" |
Compiler speed has been improved for sources generated by MATLAB*.
The compiler prevents load (ld) and store (st) instructions to be combined. For example, silicon bug workaround CPU_TC052 prevents that two ld.w instructions are combined into one ld.dw instruction.
The compiler inserts a NOP instruction between a context store operation, STUCX or STLCX, and a memory load operation which reads from the last double-word address written by the context store.
The compiler inserts a NOP instruction after each DISABLE instruction.
The compiler inserts a NOP instruction between an IP jump and CSA list instruction.
The compiler inserts a NOP instruction between any SAT.B/SAT.H instruction and a following load-store instruction with a DGPR source operand (addsc.a, addsc.at, mov.a, mtcr).
The compiler inserts two NOP instructions for a single group loop, between an IP instruction and a loop instruction targeting the IP instruction. One NOP is inserted between a LS and a loop instruction, when the single group loop exists of an optional IP instruction, a single LS instruction and a loop instruction targeting the first instruction.
The assembler checks whether an address register load instruction, LD.A or LD.DA, targeting the A[10] register, is immediately followed by an operation causing a context switch.
The assembler checks whether a context store operation, STUCX or STLCX, is immediately followed by a memory load operation which reads from the last double-word address written by the context store.
The assembler checks if the DISABLE instruction is followed by a NOP instruction
The assembler checks whether a NOP instruction is inserted between an IP jump and CSA list instruction.
The assembler checks whether a NOP instruction is inserted between any SAT.B/SAT.H instruction and a following load-store instruction with a DGPR source operand (addsc.a, addsc.at, mov.a, mtcr).
The assembler checks whether two NOP instructions are inserted for a single group loop, between an IP instruction and a loop instruction targeting the IP instruction. Furthermore the assembler checks whether one NOP is inserted between a LS and a loop instruction, when the single group loop exists of an optional IP instruction, a single LS instruction and a loop instruction targeting the first instruction.
Both the TriCore Assembler as well as the PCP assembler now support numerical labels.
Special MMU libraries have been added for derivatives that have a MMU on board. These libraries can be found in the subdirectory lib/tc1_mmu/ and lib/tc2_mmu. These MMU libraries contain a natural alignment for data objects. For example, wordsized data is wordaligned and doublewordsized data is doubleword aligned.
Please note, protected libraries for derivatives that do have a MMU (e.g. TC11xx) are also updated with this requirement of the MMU.
Using "overflow", a linker-created section size will "overflow" selected sections to another linker-created section if they do not fit in this section.
For example:
section "tsk1_data" (size=4k, attributes=rw, fill=0, overflow = "overflow_data" )
{
select ".data.tsk1.*"
}
section "tsk2_data" (size=4k, attributes=rw, fill=0, overflow = "overflow_data" )
{
select ".data.tsk2.*"
}
section "overflow_data" (size=4k, attributes=rx, fill=0)
{
}
No new/changed features.
* MATLAB is a registered trademark of The MathWorks, Inc.
Copyright 2006 Altium BV